ar5416reg.h.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

/*
 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
 * Copyright (c) 2002-2008 Atheros Communications, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 * $Id: ar5416reg.h,v 1.10 2008/11/11 00:11:30 sam Exp $
 */
#ifndef _DEV_ATH_AR5416REG_H
#define	_DEV_ATH_AR5416REG_H

#include "ar5212/ar5212reg.h"

/*
 * Register added starting with the AR5416
 */
#define	AR_MIRT			0x0020	/* interrupt rate threshold */
#define	AR_TIMT			0x0028	/* Tx Interrupt mitigation threshold */
#define	AR_RIMT			0x002C	/* Rx Interrupt mitigation threshold */
#define	AR_GTXTO		0x0064	/* global transmit timeout */
#define	AR_GTTM			0x0068	/* global transmit timeout mode */
#define	AR_CST			0x006C	/* carrier sense timeout */
#define	AR_MAC_LED		0x1f04	/* LED control */
#define	AR5416_PCIE_PM_CTRL	0x4014
#define	AR_AHB_MODE		0x4024	/* AHB mode for dma */
#define	AR_INTR_SYNC_CAUSE_CLR	0x4028	/* clear interrupt */
#define	AR_INTR_SYNC_CAUSE	0x4028	/* check pending interrupts */
#define	AR_INTR_SYNC_ENABLE	0x402c	/* enable interrupts */
#define	AR_INTR_ASYNC_MASK	0x4030	/* asynchronous interrupt mask */
#define	AR_INTR_SYNC_MASK	0x4034	/* synchronous interrupt mask */
#define	AR_INTR_ASYNC_CAUSE	0x4038	/* check pending interrupts */
#define	AR_INTR_ASYNC_ENABLE	0x403c	/* enable interrupts */
#define	AR5416_PCIE_SERDES	0x4040
#define	AR5416_PCIE_SERDES2	0x4044
#define	AR_GPIO_IN		0x4048	/* GPIO input register */
#define	AR_GPIO_INTR_OUT	0x404c	/* GPIO output register */
#define	AR_EEPROM_STATUS_DATA	0x407c
#define	AR_OBS			0x4080
#define	AR_RTC_RC		0x7000	/* reset control */
#define	AR_RTC_PLL_CONTROL	0x7014
#define	AR_RTC_RESET		0x7040	/* RTC reset register */
#define	AR_RTC_STATUS		0x7044	/* system sleep status */
#define	AR_RTC_SLEEP_CLK	0x7048
#define	AR_RTC_FORCE_WAKE	0x704c	/* control MAC force wake */
#define	AR_RTC_INTR_CAUSE	0x7050	/* RTC interrupt cause/clear */
#define	AR_RTC_INTR_ENABLE	0x7054	/* RTC interrupt enable */
#define	AR_RTC_INTR_MASK	0x7058	/* RTC interrupt mask */
/* AR9280: rf long shift registers */
#define	AR_AN_RF2G1_CH0         0x7810
#define	AR_AN_RF5G1_CH0         0x7818
#define	AR_AN_RF2G1_CH1         0x7834
#define	AR_AN_RF5G1_CH1         0x783C
#define	AR_AN_TOP2		0x7894
#define	AR_AN_SYNTH9            0x7868
#define	AR9285_AN_RF2G3         0x7828
#define	AR9285_AN_TOP3		0x786c
#define	AR_RESET_TSF		0x8020
#define	AR_RXFIFO_CFG		0x8114
#define	AR_PHY_ERR_1		0x812c
#define	AR_PHY_ERR_MASK_1	0x8130	/* mask for AR_PHY_ERR_1 */
#define	AR_PHY_ERR_2		0x8134
#define	AR_PHY_ERR_MASK_2	0x8138	/* mask for AR_PHY_ERR_2 */
#define	AR_TSFOOR_THRESHOLD	0x813c
#define	AR_PHY_ERR_3		0x8168
#define	AR_PHY_ERR_MASK_3	0x816c	/* mask for AR_PHY_ERR_3 */
#define	AR_TXOP_X		0x81ec	/* txop for legacy non-qos */
#define	AR_TXOP_0_3		0x81f0	/* txop for various tid's */
#define	AR_TXOP_4_7		0x81f4
#define	AR_TXOP_8_11		0x81f8
#define	AR_TXOP_12_15		0x81fc
/* generic timers based on tsf - all uS */
#define	AR_NEXT_TBTT		0x8200
#define	AR_NEXT_DBA		0x8204
#define	AR_NEXT_SWBA		0x8208
#define	AR_NEXT_CFP		0x8208
#define	AR_NEXT_HCF		0x820C
#define	AR_NEXT_TIM		0x8210
#define	AR_NEXT_DTIM		0x8214
#define	AR_NEXT_QUIET		0x8218
#define	AR_NEXT_NDP		0x821C
#define	AR5416_BEACON_PERIOD	0x8220
#define	AR_DBA_PERIOD		0x8224
#define	AR_SWBA_PERIOD		0x8228
#define	AR_HCF_PERIOD		0x822C
#define	AR_TIM_PERIOD		0x8230
#define	AR_DTIM_PERIOD		0x8234
#define	AR_QUIET_PERIOD		0x8238
#define	AR_NDP_PERIOD		0x823C
#define	AR_TIMER_MODE		0x8240
#define	AR_SLP32_MODE		0x8244
#define	AR_SLP32_WAKE		0x8248
#define	AR_SLP32_INC		0x824c
#define	AR_SLP_CNT		0x8250	/* 32kHz cycles with mac asleep */
#define	AR_SLP_CYCLE_CNT	0x8254	/* absolute number of 32kHz cycles */
#define	AR_SLP_MIB_CTRL		0x8258
#define	AR_2040_MODE		0x8318
#define	AR_EXTRCCNT		0x8328	/* extension channel rx clear count */
#define	AR_SELFGEN_MASK		0x832c	/* rx and cal chain masks */
#define	AR_PCU_TXBUF_CTRL	0x8340

/* DMA & PCI Registers in PCI space (usable during sleep)*/
#define	AR_RC_AHB		0x00000001	/* AHB reset */
#define	AR_RC_APB		0x00000002	/* APB reset */
#define	AR_RC_HOSTIF		0x00000100	/* host interface reset */

#define	AR_MIRT_VAL		0x0000ffff	/* in uS */
#define	AR_MIRT_VAL_S		16

#define	AR_TIMT_LAST		0x0000ffff	/* Last packet threshold */
#define	AR_TIMT_LAST_S		0
#define	AR_TIMT_FIRST		0xffff0000	/* First packet threshold */
#define	AR_TIMT_FIRST_S		16

#define	AR_RIMT_LAST		0x0000ffff	/* Last packet threshold */
#define	AR_RIMT_LAST_S		0
#define	AR_RIMT_FIRST		0xffff0000	/* First packet threshold */
#define	AR_RIMT_FIRST_S		16

#define	AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
#define	AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
#define	AR_GTXTO_TIMEOUT_LIMIT_S    16      // Shift for timeout limit

#define	AR_GTTM_USEC          0x00000001 // usec strobe
#define	AR_GTTM_IGNORE_IDLE   0x00000002 // ignore channel idle
#define	AR_GTTM_RESET_IDLE    0x00000004 // reset counter on channel idle low
#define	AR_GTTM_CST_USEC      0x00000008 // CST usec strobe

#define	AR_CST_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
#define	AR_CST_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
#define	AR_CST_TIMEOUT_LIMIT_S    16      // Shift for timeout limit

/* MAC tx DMA size config  */
#define	AR_TXCFG_DMASZ_MASK	0x00000003
#define	AR_TXCFG_DMASZ_4B	0
#define	AR_TXCFG_DMASZ_8B	1
#define	AR_TXCFG_DMASZ_16B	2
#define	AR_TXCFG_DMASZ_32B	3
#define	AR_TXCFG_DMASZ_64B	4
#define	AR_TXCFG_DMASZ_128B	5
#define	AR_TXCFG_DMASZ_256B	6
#define	AR_TXCFG_DMASZ_512B	7
#define	AR_TXCFG_ATIM_TXPOLICY	0x00000800

/* MAC rx DMA size config  */
#define	AR_RXCFG_DMASZ_MASK	0x00000007
#define	AR_RXCFG_DMASZ_4B	0
#define	AR_RXCFG_DMASZ_8B	1
#define	AR_RXCFG_DMASZ_16B	2
#define	AR_RXCFG_DMASZ_32B	3
#define	AR_RXCFG_DMASZ_64B	4
#define	AR_RXCFG_DMASZ_128B	5
#define	AR_RXCFG_DMASZ_256B	6
#define	AR_RXCFG_DMASZ_512B	7

/* MAC Led registers */
#define	AR_MAC_LED_BLINK_SLOW	0x00000008	/* LED slowest blink rate mode */
#define	AR_MAC_LED_BLINK_THRESH_SEL 0x00000070	/* LED blink threshold select */
#define	AR_MAC_LED_MODE		0x00000380	/* LED mode select */
#define	AR_MAC_LED_MODE_S	7
#define	AR_MAC_LED_MODE_PROP	0	/* Blink prop to filtered tx/rx */
#define	AR_MAC_LED_MODE_RPROP	1	/* Blink prop to unfiltered tx/rx */
#define	AR_MAC_LED_MODE_SPLIT	2	/* Blink power for tx/net for rx */
#define	AR_MAC_LED_MODE_RAND	3	/* Blink randomly */
#define	AR_MAC_LED_MODE_POWON	5	/* Power LED on (s/w control) */
#define	AR_MAC_LED_MODE_NETON	6	/* Network LED on (s/w control) */
#define	AR_MAC_LED_ASSOC	0x00000c00
#define	AR_MAC_LED_ASSOC_NONE	0x00000000 /* STA is not associated or trying */
#define	AR_MAC_LED_ASSOC_ACTIVE	0x00000400 /* STA is associated */
#define	AR_MAC_LED_ASSOC_PEND	0x00000800 /* STA is trying to associate */
#define	AR_MAC_LED_ASSOC_S	10

#define	AR_AHB_EXACT_WR_EN	0x00000000	/* write exact bytes */
#define	AR_AHB_BUF_WR_EN	0x00000001	/* buffer write upto cacheline*/
#define	AR_AHB_EXACT_RD_EN	0x00000000	/* read exact bytes */
#define	AR_AHB_CACHELINE_RD_EN	0x00000002	/* read upto end of cacheline */
#define	AR_AHB_PREFETCH_RD_EN	0x00000004	/* prefetch upto page boundary*/
#define	AR_AHB_PAGE_SIZE_1K	0x00000000	/* set page-size as 1k */
#define	AR_AHB_PAGE_SIZE_2K	0x00000008	/* set page-size as 2k */
#define	AR_AHB_PAGE_SIZE_4K	0x00000010	/* set page-size as 4k */

/* MAC PCU Registers */
#define	AR_STA_ID1_PRESERVE_SEQNUM	0x20000000 /* Don't replace seq num */

/* Extended PCU DIAG_SW control fields */
#define	AR_DIAG_DUAL_CHAIN_INFO	0x01000000	/* dual chain channel info */
#define	AR_DIAG_RX_ABORT	0x02000000	/* abort rx */
#define	AR_DIAG_SATURATE_CCNT	0x04000000	/* sat. cycle cnts (no shift) */
#define	AR_DIAG_OBS_PT_SEL2	0x08000000	/* observation point sel */
#define	AR_DIAG_RXCLEAR_CTL_LOW	0x10000000	/* force rx_clear(ctl) low/busy */
#define	AR_DIAG_RXCLEAR_EXT_LOW	0x20000000	/* force rx_clear(ext) low/busy */

#define	AR_TXOP_X_VAL	0x000000FF

#define	AR_RESET_TSF_ONCE	0x01000000	/* reset tsf once; self-clears*/

/* Interrupts */
#define	AR_ISR_TXMINTR		0x00080000	/* Maximum interrupt tx rate */
#define	AR_ISR_RXMINTR		0x01000000	/* Maximum interrupt rx rate */
#define	AR_ISR_TXINTM		0x40000000	/* Tx int after mitigation */
#define	AR_ISR_RXINTM		0x80000000	/* Rx int after mitigation */

#define	AR_ISR_S2_CST		0x00400000	/* Carrier sense timeout */
#define	AR_ISR_S2_GTT		0x00800000	/* Global transmit timeout */
#define	AR_ISR_S2_TSFOOR	0x40000000	/* RX TSF out of range */

#define	AR_INTR_SPURIOUS	0xffffffff
#define	AR_INTR_RTC_IRQ		0x00000001	/* rtc in shutdown state */
#define	AR_INTR_MAC_IRQ		0x00000002	/* pending mac interrupt */
#define	AR_INTR_EEP_PROT_ACCESS	0x00000004	/* eeprom protected access */
#define	AR_INTR_MAC_AWAKE	0x00020000	/* mac is awake */
#define	AR_INTR_MAC_ASLEEP	0x00040000	/* mac is asleep */

/* Interrupt Mask Registers */
#define	AR_IMR_TXMINTR		0x00080000	/* Maximum interrupt tx rate */
#define	AR_IMR_RXMINTR		0x01000000	/* Maximum interrupt rx rate */
#define	AR_IMR_TXINTM		0x40000000	/* Tx int after mitigation */
#define	AR_IMR_RXINTM		0x80000000	/* Rx int after mitigation */

#define	AR_IMR_S2_CST		0x00400000	/* Carrier sense timeout */
#define	AR_IMR_S2_GTT		0x00800000	/* Global transmit timeout */

/* synchronous interrupt signals */
#define	AR_INTR_SYNC_RTC_IRQ		0x00000001
#define	AR_INTR_SYNC_MAC_IRQ		0x00000002
#define	AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS	0x00000004
#define	AR_INTR_SYNC_APB_TIMEOUT	0x00000008
#define	AR_INTR_SYNC_PCI_MODE_CONFLICT	0x00000010
#define	AR_INTR_SYNC_HOST1_FATAL	0x00000020
#define	AR_INTR_SYNC_HOST1_PERR		0x00000040
#define	AR_INTR_SYNC_TRCV_FIFO_PERR	0x00000080
#define	AR_INTR_SYNC_RADM_CPL_EP	0x00000100
#define	AR_INTR_SYNC_RADM_CPL_DLLP_ABORT	0x00000200
#define	AR_INTR_SYNC_RADM_CPL_TLP_ABORT	0x00000400
#define	AR_INTR_SYNC_RADM_CPL_ECRC_ERR	0x00000800
#define	AR_INTR_SYNC_RADM_CPL_TIMEOUT	0x00001000
#define	AR_INTR_SYNC_LOCAL_TIMEOUT	0x00002000
#define	AR_INTR_SYNC_PM_ACCESS		0x00004000
#define	AR_INTR_SYNC_MAC_AWAKE		0x00008000
#define	AR_INTR_SYNC_MAC_ASLEEP		0x00010000
#define	AR_INTR_SYNC_MAC_SLEEP_ACCESS	0x00020000
#define	AR_INTR_SYNC_ALL		0x0003FFFF

/* default synchronous interrupt signals enabled */
#define	AR_INTR_SYNC_DEFAULT \