ar5211reg.h.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

#define	AR_D_MISC_HCF_POLL_EN	0x00000800	/* HFC poll enable */
#define	AR_D_MISC_BKOFF_PERSISTENCE	0x00001000	/* Backoff persistence factor setting */
#define	AR_D_MISC_FR_PREFETCH_EN	0x00002000	/* Frame prefetch enable */
#define	AR_D_MISC_VIR_COL_HANDLING_M	0x0000C000	/* Mask for Virtual collision handling policy */
#define	AR_D_MISC_VIR_COL_HANDLING_NORMAL	0     	/* Normal */
#define	AR_D_MISC_VIR_COL_HANDLING_MODIFIED	1   	/* Modified */
#define	AR_D_MISC_VIR_COL_HANDLING_IGNORE	2     	/* Ignore */
#define	AR_D_MISC_BEACON_USE	0x00010000	/* Beacon use indication */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL	0x00060000	/* Mask for DCU arbiter lockout control */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_S	17        	/* Shift for DCU arbiter lockout control */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE	0      	/* No lockout */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR	1  	/* Intra-frame */
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL	2    	/* Global */
#define	AR_D_MISC_ARB_LOCKOUT_IGNORE	0x00080000	/* DCU arbiter lockout ignore control */
#define	AR_D_MISC_SEQ_NUM_INCR_DIS	0x00100000	/* Sequence number increment disable */
#define	AR_D_MISC_POST_FR_BKOFF_DIS	0x00200000	/* Post-frame backoff disable */
#define	AR_D_MISC_VIRT_COLL_POLICY	0x00400000	/* Virtual coll. handling policy */
#define	AR_D_MISC_BLOWN_IFS_POLICY	0x00800000	/* Blown IFS handling policy */
#define	AR5311_D_MISC_SEQ_NUM_CONTROL	0x01000000	/* Sequence Number local or global */
						/* Maui2/Spirit only, reserved on Oahu */
#define	AR_D_MISC_RESV0	0xFE000000	/* Reserved */

#define	AR_D_SEQNUM_M	0x00000FFF	/* Mask for value of sequence number */
#define	AR_D_SEQNUM_RESV0	0xFFFFF000	/* Reserved */

#define	AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL	0x00000007	/* Mask forLFSR slice select */
#define	AR_D_GBL_IFS_MISC_TURBO_MODE	0x00000008	/* Turbo mode indication */
#define	AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC	0x000003F0	/* Mask for SIFS duration (us) */
#define	AR_D_GBL_IFS_MISC_USEC_DURATION	0x000FFC00	/* Mask for microsecond duration */
#define	AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY	0x00300000	/* Mask for DCU arbiter delay */
#define	AR_D_GBL_IFS_MISC_RESV0	0xFFC00000	/* Reserved */

/* Oahu only */
#define	AR_D_TXPSE_CTRL_M	0x000003FF	/* Mask of DCUs to pause (DCUs 0-9) */
#define	AR_D_TXPSE_RESV0	0x0000FC00	/* Reserved */
#define	AR_D_TXPSE_STATUS	0x00010000	/* Transmit pause status */
#define	AR_D_TXPSE_RESV1	0xFFFE0000	/* Reserved */

	/* DMA & PCI Registers in PCI space (usable during sleep) */
#define	AR_RC_MAC	0x00000001	/* MAC reset */
#define	AR_RC_BB	0x00000002	/* Baseband reset */
#define	AR_RC_RESV0	0x00000004	/* Reserved */
#define	AR_RC_RESV1	0x00000008	/* Reserved */
#define	AR_RC_PCI	0x00000010	/* PCI-core reset */
#define	AR_RC_BITS	"\20\1MAC\2BB\3RESV0\4RESV1\5RPCI"

#define	AR_SCR_SLDUR	0x0000ffff	/* sleep duration mask, units of 128us */
#define	AR_SCR_SLDUR_S	0
#define	AR_SCR_SLE	0x00030000	/* sleep enable mask */
#define	AR_SCR_SLE_S	16		/* sleep enable bits shift */
#define	AR_SCR_SLE_WAKE	0x00000000	/* force wake */
#define	AR_SCR_SLE_SLP	0x00010000	/* force sleep */
#define	AR_SCR_SLE_NORM	0x00020000	/* sleep logic normal operation */
#define	AR_SCR_SLE_UNITS	0x00000008	/* SCR units/TU */
#define	AR_SCR_BITS	"\20\20SLE_SLP\21SLE"

#define	AR_INTPEND_TRUE	0x00000001	/* interrupt pending */
#define	AR_INTPEND_BITS	"\20\1IP"

#define	AR_SFR_SLEEP	0x00000001	/* force sleep */

#define	AR_PCICFG_CLKRUNEN	0x00000004	/* enable PCI CLKRUN function */
#define	AR_PCICFG_EEPROM_SIZE_M	0x00000018	/* Mask for EEPROM size */
#define	AR_PCICFG_EEPROM_SIZE_S	  3	/* Mask for EEPROM size */
#define	AR_PCICFG_EEPROM_SIZE_4K	 0	/* EEPROM size 4 Kbit */
#define	AR_PCICFG_EEPROM_SIZE_8K	 1	/* EEPROM size 8 Kbit */
#define	AR_PCICFG_EEPROM_SIZE_16K	2	/* EEPROM size 16 Kbit */
#define	AR_PCICFG_EEPROM_SIZE_FAILED	3	/* Failure */
#define	AR_PCICFG_LEDCTL	0x00000060 /* LED control Status */
#define	AR_PCICFG_LEDCTL_NONE	0x00000000 /* STA is not associated or trying */
#define	AR_PCICFG_LEDCTL_PEND	0x00000020 /* STA is trying to associate */
#define	AR_PCICFG_LEDCTL_ASSOC	0x00000040 /* STA is associated */
#define	AR_PCICFG_PCI_BUS_SEL_M	0x00000380	/* Mask for PCI observation bus mux select */
#define	AR_PCICFG_DIS_CBE_FIX	0x00000400	/* Disable fix for bad PCI CBE# generation */
#define	AR_PCICFG_SL_INTEN	0x00000800	/* enable interrupt line assertion when asleep */
#define	AR_PCICFG_RESV0		0x00001000	/* Reserved */
#define	AR_PCICFG_SL_INPEN	0x00002000	/* Force asleep when an interrupt is pending */
#define	AR_PCICFG_RESV1		0x0000C000	/* Reserved */
#define	AR_PCICFG_SPWR_DN	0x00010000	/* mask for sleep/awake indication */
#define	AR_PCICFG_LEDMODE	0x000E0000 /* LED mode */
#define	AR_PCICFG_LEDMODE_PROP	0x00000000 /* Blink prop to filtered tx/rx */
#define	AR_PCICFG_LEDMODE_RPROP	0x00020000 /* Blink prop to unfiltered tx/rx */
#define	AR_PCICFG_LEDMODE_SPLIT	0x00040000 /* Blink power for tx/net for rx */
#define	AR_PCICFG_LEDMODE_RAND	0x00060000 /* Blink randomly */
#define	AR_PCICFG_LEDBLINK	0x00700000 /* LED blink threshold select */
#define	AR_PCICFG_LEDBLINK_S	20
#define	AR_PCICFG_LEDSLOW	0x00800000 /* LED slowest blink rate mode */
#define	AR_PCICFG_RESV2		0xFF000000	/* Reserved */
#define	AR_PCICFG_BITS	"\20\3CLKRUNEN\13SL_INTEN"

#define	AR_GPIOCR_CR_SHIFT	2         	/* Each CR is 2 bits */
#define	AR_GPIOCR_0_CR_N	0x00000000	/* Input only mode for GPIODO[0] */
#define	AR_GPIOCR_0_CR_0	0x00000001	/* Output only if GPIODO[0] = 0 */
#define	AR_GPIOCR_0_CR_1	0x00000002	/* Output only if GPIODO[0] = 1 */
#define	AR_GPIOCR_0_CR_A	0x00000003	/* Always output */
#define	AR_GPIOCR_1_CR_N	0x00000000	/* Input only mode for GPIODO[1] */
#define	AR_GPIOCR_1_CR_0	0x00000004	/* Output only if GPIODO[1] = 0 */
#define	AR_GPIOCR_1_CR_1	0x00000008	/* Output only if GPIODO[1] = 1 */
#define	AR_GPIOCR_1_CR_A	0x0000000C	/* Always output */
#define	AR_GPIOCR_2_CR_N	0x00000000	/* Input only mode for GPIODO[2] */
#define	AR_GPIOCR_2_CR_0	0x00000010	/* Output only if GPIODO[2] = 0 */
#define	AR_GPIOCR_2_CR_1	0x00000020	/* Output only if GPIODO[2] = 1 */
#define	AR_GPIOCR_2_CR_A	0x00000030	/* Always output */
#define	AR_GPIOCR_3_CR_N	0x00000000	/* Input only mode for GPIODO[3] */
#define	AR_GPIOCR_3_CR_0	0x00000040	/* Output only if GPIODO[3] = 0 */
#define	AR_GPIOCR_3_CR_1	0x00000080	/* Output only if GPIODO[3] = 1 */
#define	AR_GPIOCR_3_CR_A	0x000000C0	/* Always output */
#define	AR_GPIOCR_4_CR_N	0x00000000	/* Input only mode for GPIODO[4] */
#define	AR_GPIOCR_4_CR_0	0x00000100	/* Output only if GPIODO[4] = 0 */
#define	AR_GPIOCR_4_CR_1	0x00000200	/* Output only if GPIODO[4] = 1 */
#define	AR_GPIOCR_4_CR_A	0x00000300	/* Always output */
#define	AR_GPIOCR_5_CR_N	0x00000000	/* Input only mode for GPIODO[5] */
#define	AR_GPIOCR_5_CR_0	0x00000400	/* Output only if GPIODO[5] = 0 */
#define	AR_GPIOCR_5_CR_1	0x00000800	/* Output only if GPIODO[5] = 1 */
#define	AR_GPIOCR_5_CR_A	0x00000C00	/* Always output */
#define	AR_GPIOCR_INT_SHIFT	12        	/* Interrupt select field shifter */
#define	AR_GPIOCR_INT_MASK	0x00007000	/* Interrupt select field mask */
#define	AR_GPIOCR_INT_SEL0	0x00000000	/* Select Interrupt Pin GPIO_0 */
#define	AR_GPIOCR_INT_SEL1	0x00001000	/* Select Interrupt Pin GPIO_1 */
#define	AR_GPIOCR_INT_SEL2	0x00002000	/* Select Interrupt Pin GPIO_2 */
#define	AR_GPIOCR_INT_SEL3	0x00003000	/* Select Interrupt Pin GPIO_3 */
#define	AR_GPIOCR_INT_SEL4	0x00004000	/* Select Interrupt Pin GPIO_4 */
#define	AR_GPIOCR_INT_SEL5	0x00005000	/* Select Interrupt Pin GPIO_5 */
#define	AR_GPIOCR_INT_ENA	0x00008000	/* Enable GPIO Interrupt */
#define	AR_GPIOCR_INT_SELL	0x00000000	/* Generate Interrupt if selected pin is low */
#define	AR_GPIOCR_INT_SELH	0x00010000	/* Generate Interrupt if selected pin is high */

#define	AR_SREV_ID_M	0x000000FF	/* Mask to read SREV info */
#define	AR_PCICFG_EEPROM_SIZE_16K	2	/* EEPROM size 16 Kbit */
#define	AR_SREV_ID_S		4		/* Major Rev Info */
#define	AR_SREV_REVISION_M	0x0000000F	/* Chip revision level */
#define	AR_SREV_FPGA		1
#define	AR_SREV_D2PLUS		2
#define	AR_SREV_D2PLUS_MS	3		/* metal spin */
#define	AR_SREV_CRETE		4
#define	AR_SREV_CRETE_MS	5		/* FCS metal spin */
#define	AR_SREV_CRETE_MS23	7		/* 2.3 metal spin (6 skipped) */
#define	AR_SREV_CRETE_23	8		/* 2.3 full tape out */
#define	AR_SREV_VERSION_M	0x000000F0	/* Chip version indication */
#define	AR_SREV_VERSION_CRETE	0
#define	AR_SREV_VERSION_MAUI_1	1
#define	AR_SREV_VERSION_MAUI_2	2
#define	AR_SREV_VERSION_SPIRIT	3
#define	AR_SREV_VERSION_OAHU	4
#define	AR_SREV_OAHU_ES		0	/* Engineering Sample */
#define	AR_SREV_OAHU_PROD	2	/* Production */

#define	RAD5_SREV_MAJOR	0x10	/* All current supported ar5211 5 GHz radios are rev 0x10 */
#define	RAD5_SREV_PROD	0x15	/* Current production level radios */
#define	RAD2_SREV_MAJOR	0x20	/* All current supported ar5211 2 GHz radios are rev 0x10 */

	/* EEPROM Registers in the MAC */
#define	AR_EEPROM_CMD_READ	0x00000001
#define	AR_EEPROM_CMD_WRITE	0x00000002
#define	AR_EEPROM_CMD_RESET	0x00000004

#define	AR_EEPROM_STS_READ_ERROR	0x00000001
#define	AR_EEPROM_STS_READ_COMPLETE	0x00000002
#define	AR_EEPROM_STS_WRITE_ERROR	0x00000004
#define	AR_EEPROM_STS_WRITE_COMPLETE	0x00000008

#define	AR_EEPROM_CFG_SIZE_M	0x00000003	/* Mask for EEPROM size determination override */
#define	AR_EEPROM_CFG_SIZE_AUTO	0
#define	AR_EEPROM_CFG_SIZE_4KBIT	1
#define	AR_EEPROM_CFG_SIZE_8KBIT	2
#define	AR_EEPROM_CFG_SIZE_16KBIT	3
#define	AR_EEPROM_CFG_DIS_WAIT_WRITE_COMPL	0x00000004	/* Disable wait for write completion */
#define	AR_EEPROM_CFG_CLOCK_M	0x00000018	/* Mask for EEPROM clock rate control */
#define	AR_EEPROM_CFG_CLOCK_S	3        	/* Shift for EEPROM clock rate control */
#define	AR_EEPROM_CFG_CLOCK_156KHZ	0
#define	AR_EEPROM_CFG_CLOCK_312KHZ	1
#define	AR_EEPROM_CFG_CLOCK_625KHZ	2
#define	AR_EEPROM_CFG_RESV0	0x000000E0	/* Reserved */
#define	AR_EEPROM_CFG_PROT_KEY_M	0x00FFFF00	/* Mask for EEPROM protection key */
#define	AR_EEPROM_CFG_PROT_KEY_S	8          	/* Shift for EEPROM protection key */
#define	AR_EEPROM_CFG_EN_L	0x01000000	/* EPRM_EN_L setting */

	/* MAC PCU Registers */
#define	AR_STA_ID1_SADH_MASK	0x0000FFFF	/* Mask for upper 16 bits of MAC addr */
#define	AR_STA_ID1_STA_AP	0x00010000	/* Device is AP */
#define	AR_STA_ID1_ADHOC	0x00020000	/* Device is ad-hoc */
#define	AR_STA_ID1_PWR_SAV	0x00040000	/* Power save reporting in self-generated frames */
#define	AR_STA_ID1_KSRCHDIS	0x00080000	/* Key search disable */
#define	AR_STA_ID1_PCF	0x00100000	/* Observe PCF */
#define	AR_STA_ID1_DEFAULT_ANTENNA	0x00200000	/* Use default antenna */
#define	AR_STA_ID1_DESC_ANTENNA	0x00400000	/* Update default antenna w/ TX antenna */
#define	AR_STA_ID1_RTS_USE_DEF	0x00800000	/* Use default antenna to send RTS */
#define	AR_STA_ID1_ACKCTS_6MB	0x01000000	/* Use 6Mb/s rate for ACK & CTS */
#define	AR_STA_ID1_BASE_RATE_11B	0x02000000	/* Use 11b base rate for ACK & CTS */
#define	AR_STA_ID1_BITS \
	"\20\20AP\21ADHOC\22PWR_SAV\23KSRCHDIS\25PCF"

#define	AR_BSS_ID1_U16_M	0x0000FFFF	/* Mask for upper 16 bits of BSSID */
#define	AR_BSS_ID1_AID_M	0xFFFF0000	/* Mask for association ID */
#define	AR_BSS_ID1_AID_S	16       	/* Shift for association ID */

#define	AR_SLOT_TIME_MASK	0x000007FF	/* Slot time mask */

#define	AR_TIME_OUT_ACK		0x00001FFF	/* Mask for ACK time-out */
#define	AR_TIME_OUT_ACK_S	0		/* Shift for ACK time-out */
#define	AR_TIME_OUT_CTS		0x1FFF0000	/* Mask for CTS time-out */
#define	AR_TIME_OUT_CTS_S	16       	/* Shift for CTS time-out */

#define	AR_RSSI_THR_MASK	0x000000FF	/* Mask for Beacon RSSI warning threshold */
#define	AR_RSSI_THR_BM_THR	0x0000FF00	/* Mask for Missed beacon threshold */
#define	AR_RSSI_THR_BM_THR_S	8        	/* Shift for Missed beacon threshold */

#define	AR_USEC_M	0x0000007F		/* Mask for clock cycles in 1 usec */
#define	AR_USEC_32_M	0x00003F80		/* Mask for number of 32MHz clock cycles in 1 usec */
#define	AR_USEC_32_S	7			/* Shift for number of 32MHz clock cycles in 1 usec */
/*
 * Tx/Rx latencies are to signal start and are in usecs.
 *
 * NOTE: AR5211/AR5311 difference: on Oahu, the TX latency field
 *       has increased from 6 bits to 9 bits.  The RX latency field
 *	 is unchanged, but is shifted over 3 bits.
 */
#define	AR5311_USEC_TX_LAT_M	0x000FC000	/* Tx latency */
#define	AR5311_USEC_TX_LAT_S	14
#define	AR5311_USEC_RX_LAT_M	0x03F00000	/* Rx latency */
#define	AR5311_USEC_RX_LAT_S	20

#define	AR5211_USEC_TX_LAT_M	0x007FC000	/* Tx latency */
#define	AR5211_USEC_TX_LAT_S	14
#define	AR5211_USEC_RX_LAT_M	0x1F800000	/* Rx latency */
#define	AR5211_USEC_RX_LAT_S	23


#define	AR_BEACON_PERIOD	0x0000FFFF	/* Beacon period in TU/msec */
#define	AR_BEACON_PERIOD_S	0		/* Byte offset of PERIOD start*/
#define	AR_BEACON_TIM		0x007F0000	/* Byte offset of TIM start */
#define	AR_BEACON_TIM_S		16        	/* Byte offset of TIM start */
#define	AR_BEACON_EN		0x00800000	/* beacon enable */
#define	AR_BEACON_RESET_TSF	0x01000000	/* Clears TSF to 0 */
#define	AR_BEACON_BITS	"\20\27ENABLE\30RESET_TSF"

#define	AR_RX_FILTER_ALL	0x00000000	/* Disallow all frames */
#define	AR_RX_UCAST		0x00000001	/* Allow unicast frames */
#define	AR_RX_MCAST		0x00000002	/* Allow multicast frames */
#define	AR_RX_BCAST		0x00000004	/* Allow broadcast frames */
#define	AR_RX_CONTROL		0x00000008	/* Allow control frames */
#define	AR_RX_BEACON		0x00000010	/* Allow beacon frames */
#define	AR_RX_PROM		0x00000020	/* Promiscuous mode */
#define	AR_RX_PHY_ERR		0x00000040	/* Allow all phy errors */
#define	AR_RX_PHY_RADAR		0x00000080	/* Allow radar phy errors */
#define	AR_RX_FILTER_BITS \
	"\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC\7PHY_ERR\10PHY_RADAR"

#define	AR_DIAG_SW_CACHE_ACK	0x00000001	/* disable ACK if no valid key*/
#define	AR_DIAG_SW_DIS_ACK	0x00000002	/* disable ACK generation */
#define	AR_DIAG_SW_DIS_CTS	0x00000004	/* disable CTS generation */
#define	AR_DIAG_SW_DIS_ENCRYPT	0x00000008	/* disable encryption */
#define	AR_DIAG_SW_DIS_DECRYPT	0x00000010	/* disable decryption */
#define	AR_DIAG_SW_DIS_RX	0x00000020	/* disable receive */
#define	AR_DIAG_SW_CORR_FCS	0x00000080	/* corrupt FCS */
#define	AR_DIAG_SW_CHAN_INFO	0x00000100	/* dump channel info */
#define	AR_DIAG_SW_EN_SCRAMSD	0x00000200	/* enable fixed scrambler seed*/
#define	AR5311_DIAG_SW_USE_ECO	0x00000400	/* "super secret" use ECO enable bit */
#define	AR_DIAG_SW_SCRAM_SEED_M	0x0001FC00	/* Fixed scrambler seed mask */
#define	AR_DIAG_SW_SCRAM_SEED_S	10       	/* Fixed scrambler seed shfit */
#define	AR_DIAG_SW_FRAME_NV0	0x00020000	/* accept frames of non-zero protocol version */
#define	AR_DIAG_SW_OBS_PT_SEL_M	0x000C0000	/* Observation point select */
#define	AR_DIAG_SW_OBS_PT_SEL_S	18       	/* Observation point select */
#define	AR_DIAG_SW_BITS \
	"\20\1DIS_CACHE_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_RX"\
	"\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED\14USE_ECO\24FRAME_NV0"

#define	AR_KEYTABLE_KEY0(n)	(AR_KEYTABLE(n) + 0)	/* key bit 0-31 */
#define	AR_KEYTABLE_KEY1(n)	(AR_KEYTABLE(n) + 4)	/* key bit 32-47 */
#define	AR_KEYTABLE_KEY2(n)	(AR_KEYTABLE(n) + 8)	/* key bit 48-79 */
#define	AR_KEYTABLE_KEY3(n)	(AR_KEYTABLE(n) + 12)	/* key bit 80-95 */
#define	AR_KEYTABLE_KEY4(n)	(AR_KEYTABLE(n) + 16)	/* key bit 96-127 */
#define	AR_KEYTABLE_TYPE(n)	(AR_KEYTABLE(n) + 20)	/* key type */
#define	AR_KEYTABLE_TYPE_40	0x00000000	/* WEP 40 bit key */
#define	AR_KEYTABLE_TYPE_104	0x00000001	/* WEP 104 bit key */
#define	AR_KEYTABLE_TYPE_128	0x00000003	/* WEP 128 bit key */
#define	AR_KEYTABLE_TYPE_AES	0x00000005	/* AES 128 bit key */
#define	AR_KEYTABLE_TYPE_CLR	0x00000007	/* no encryption */
#define	AR_KEYTABLE_MAC0(n)	(AR_KEYTABLE(n) + 24)	/* MAC address 1-32 */
#define	AR_KEYTABLE_MAC1(n)	(AR_KEYTABLE(n) + 28)	/* MAC address 33-47 */
#define	AR_KEYTABLE_VALID	0x00008000	/* key and MAC address valid */

#endif /* _DEV_ATH_AR5211REG_H */