ar5211reg.h.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

#define	AR_CFG_CLK_GATE_DIS	0x00000400	/* Clock gating disable (Oahu only) */
#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_M	0x00060000	/* Mask of PCI core master request queue full threshold */
#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_S	17        	/* Shift for PCI core master request queue full threshold */
#define	AR_CFG_BITS \
	"\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\10PHYOK11EEBS"

#define	AR_IER_ENABLE	0x00000001	/* Global interrupt enable */
#define	AR_IER_DISABLE	0x00000000	/* Global interrupt disable */
#define	AR_IER_BITS	"\20\1ENABLE"

#define	AR_RTSD0_RTS_DURATION_6_M	0x000000FF
#define	AR_RTSD0_RTS_DURATION_6_S	0
#define	AR_RTSD0_RTS_DURATION_9_M	0x0000FF00
#define	AR_RTSD0_RTS_DURATION_9_S	8
#define	AR_RTSD0_RTS_DURATION_12_M	0x00FF0000
#define	AR_RTSD0_RTS_DURATION_12_S	16
#define	AR_RTSD0_RTS_DURATION_18_M	0xFF000000
#define	AR_RTSD0_RTS_DURATION_18_S	24

#define	AR_RTSD0_RTS_DURATION_24_M	0x000000FF
#define	AR_RTSD0_RTS_DURATION_24_S	0
#define	AR_RTSD0_RTS_DURATION_36_M	0x0000FF00
#define	AR_RTSD0_RTS_DURATION_36_S	8
#define	AR_RTSD0_RTS_DURATION_48_M	0x00FF0000
#define	AR_RTSD0_RTS_DURATION_48_S	16
#define	AR_RTSD0_RTS_DURATION_54_M	0xFF000000
#define	AR_RTSD0_RTS_DURATION_54_S	24

#define	AR_DMASIZE_4B	0x00000000	/* DMA size 4 bytes (TXCFG + RXCFG) */
#define	AR_DMASIZE_8B	0x00000001	/* DMA size 8 bytes */
#define	AR_DMASIZE_16B	0x00000002	/* DMA size 16 bytes */
#define	AR_DMASIZE_32B	0x00000003	/* DMA size 32 bytes */
#define	AR_DMASIZE_64B	0x00000004	/* DMA size 64 bytes */
#define	AR_DMASIZE_128B	0x00000005	/* DMA size 128 bytes */
#define	AR_DMASIZE_256B	0x00000006	/* DMA size 256 bytes */
#define	AR_DMASIZE_512B	0x00000007	/* DMA size 512 bytes */

#define	AR_TXCFG_FTRIG_M	0x000003F0	/* Mask for Frame trigger level */
#define	AR_TXCFG_FTRIG_S	4         	/* Shift for Frame trigger level */
#define	AR_TXCFG_FTRIG_IMMED	0x00000000	/* bytes in PCU TX FIFO before air */
#define	AR_TXCFG_FTRIG_64B	0x00000010	/* default */
#define	AR_TXCFG_FTRIG_128B	0x00000020
#define	AR_TXCFG_FTRIG_192B	0x00000030
#define	AR_TXCFG_FTRIG_256B	0x00000040	/* 5 bits total */
#define	AR_TXCFG_BITS	"\20"

#define	AR5311_RXCFG_DEF_RX_ANTENNA	0x00000008	/* Default Receive Antenna */
						/* Maui2/Spirit only - reserved on Oahu */
#define	AR_RXCFG_ZLFDMA	0x00000010	/* Enable DMA of zero-length frame */
#define	AR_RXCFG_EN_JUM	0x00000020	/* Enable jumbo rx descriptors */
#define	AR_RXCFG_WR_JUM	0x00000040	/* Wrap jumbo rx descriptors */

#define	AR_MIBC_COW	0x00000001	/* counter overflow warning */
#define	AR_MIBC_FMC	0x00000002	/* freeze MIB counters */
#define	AR_MIBC_CMC	0x00000004	/* clear MIB counters */
#define	AR_MIBC_MCS	0x00000008	/* MIB counter strobe, increment all */

#define	AR_TOPS_MASK	0x0000FFFF	/* Mask for timeout prescale */

#define	AR_RXNPTO_MASK	0x000003FF	/* Mask for no frame received timeout */

#define	AR_TXNPTO_MASK	0x000003FF	/* Mask for no frame transmitted timeout */
#define	AR_TXNPTO_QCU_MASK	0x03FFFC00	/* Mask indicating the set of QCUs */
					/* for which frame completions will cause */
					/* a reset of the no frame transmitted timeout */

#define	AR_RPGTO_MASK	0x000003FF	/* Mask for receive frame gap timeout */

#define	AR_RPCNT_MASK	0x0000001F	/* Mask for receive frame count limit */

#define	AR_MACMISC_DMA_OBS_M	0x000001E0	/* Mask for DMA observation bus mux select */
#define	AR_MACMISC_DMA_OBS_S	5         	/* Shift for DMA observation bus mux select */
#define	AR_MACMISC_MISC_OBS_M	0x00000E00	/* Mask for MISC observation bus mux select */
#define	AR_MACMISC_MISC_OBS_S	9         	/* Shift for MISC observation bus mux select */
#define	AR_MACMISC_MAC_OBS_BUS_LSB_M	0x00007000	/* Mask for MAC observation bus mux select (lsb) */
#define	AR_MACMISC_MAC_OBS_BUS_LSB_S	12        	/* Shift for MAC observation bus mux select (lsb) */
#define	AR_MACMISC_MAC_OBS_BUS_MSB_M	0x00038000	/* Mask for MAC observation bus mux select (msb) */
#define	AR_MACMISC_MAC_OBS_BUS_MSB_S	15        	/* Shift for MAC observation bus mux select (msb) */

				/* Maui2/Spirit only. */
#define	AR5311_QDCLKGATE_QCU_M	0x0000FFFF	/* Mask for QCU clock disable */
#define	AR5311_QDCLKGATE_DCU_M	0x07FF0000	/* Mask for DCU clock disable */

	/* Interrupt Status Registers */
#define	AR_ISR_RXOK	0x00000001	/* At least one frame received sans errors */
#define	AR_ISR_RXDESC	0x00000002	/* Receive interrupt request */
#define	AR_ISR_RXERR	0x00000004	/* Receive error interrupt */
#define	AR_ISR_RXNOPKT	0x00000008	/* No frame received within timeout clock */
#define	AR_ISR_RXEOL	0x00000010	/* Received descriptor empty interrupt */
#define	AR_ISR_RXORN	0x00000020	/* Receive FIFO overrun interrupt */
#define	AR_ISR_TXOK	0x00000040	/* Transmit okay interrupt */
#define	AR_ISR_TXDESC	0x00000080	/* Transmit interrupt request */
#define	AR_ISR_TXERR	0x00000100	/* Transmit error interrupt */
#define	AR_ISR_TXNOPKT	0x00000200	/* No frame transmitted interrupt */
#define	AR_ISR_TXEOL	0x00000400	/* Transmit descriptor empty interrupt */
#define	AR_ISR_TXURN	0x00000800	/* Transmit FIFO underrun interrupt */
#define	AR_ISR_MIB	0x00001000	/* MIB interrupt - see MIBC */
#define	AR_ISR_SWI	0x00002000	/* Software interrupt */
#define	AR_ISR_RXPHY	0x00004000	/* PHY receive error interrupt */
#define	AR_ISR_RXKCM	0x00008000	/* Key-cache miss interrupt */
#define	AR_ISR_SWBA	0x00010000	/* Software beacon alert interrupt */
#define	AR_ISR_BRSSI	0x00020000	/* Beacon threshold interrupt */
#define	AR_ISR_BMISS	0x00040000	/* Beacon missed interrupt */
#define	AR_ISR_HIUERR	0x00080000	/* An unexpected bus error has occurred */
#define	AR_ISR_BNR	0x00100000	/* Beacon not ready interrupt */
#define	AR_ISR_TIM	0x00800000	/* TIM interrupt */
#define	AR_ISR_GPIO	0x01000000	/* GPIO Interrupt */
#define	AR_ISR_QCBROVF	0x02000000	/* QCU CBR overflow interrupt */
#define	AR_ISR_QCBRURN	0x04000000	/* QCU CBR underrun interrupt */
#define	AR_ISR_QTRIG	0x08000000	/* QCU scheduling trigger interrupt */
#define	AR_ISR_RESV0	0xF0000000	/* Reserved */

#define	AR_ISR_S0_QCU_TXOK_M	0x000003FF	/* Mask for TXOK (QCU 0-9) */
#define	AR_ISR_S0_QCU_TXDESC_M	0x03FF0000	/* Mask for TXDESC (QCU 0-9) */

#define	AR_ISR_S1_QCU_TXERR_M	0x000003FF	/* Mask for TXERR (QCU 0-9) */
#define	AR_ISR_S1_QCU_TXEOL_M	0x03FF0000	/* Mask for TXEOL (QCU 0-9) */

#define	AR_ISR_S2_QCU_TXURN_M	0x000003FF	/* Mask for TXURN (QCU 0-9) */
#define	AR_ISR_S2_MCABT	0x00010000	/* Master cycle abort interrupt */
#define	AR_ISR_S2_SSERR	0x00020000	/* SERR interrupt */
#define	AR_ISR_S2_DPERR	0x00040000	/* PCI bus parity error */
#define	AR_ISR_S2_RESV0	0xFFF80000	/* Reserved */

#define	AR_ISR_S3_QCU_QCBROVF_M	0x000003FF	/* Mask for QCBROVF (QCU 0-9) */
#define	AR_ISR_S3_QCU_QCBRURN_M	0x03FF0000	/* Mask for QCBRURN (QCU 0-9) */

#define	AR_ISR_S4_QCU_QTRIG_M	0x000003FF	/* Mask for QTRIG (QCU 0-9) */
#define	AR_ISR_S4_RESV0	0xFFFFFC00	/* Reserved */

	/* Interrupt Mask Registers */
#define	AR_IMR_RXOK	0x00000001	/* At least one frame received sans errors */
#define	AR_IMR_RXDESC	0x00000002	/* Receive interrupt request */
#define	AR_IMR_RXERR	0x00000004	/* Receive error interrupt */
#define	AR_IMR_RXNOPKT	0x00000008	/* No frame received within timeout clock */
#define	AR_IMR_RXEOL	0x00000010	/* Received descriptor empty interrupt */
#define	AR_IMR_RXORN	0x00000020	/* Receive FIFO overrun interrupt */
#define	AR_IMR_TXOK	0x00000040	/* Transmit okay interrupt */
#define	AR_IMR_TXDESC	0x00000080	/* Transmit interrupt request */
#define	AR_IMR_TXERR	0x00000100	/* Transmit error interrupt */
#define	AR_IMR_TXNOPKT	0x00000200	/* No frame transmitted interrupt */
#define	AR_IMR_TXEOL	0x00000400	/* Transmit descriptor empty interrupt */
#define	AR_IMR_TXURN	0x00000800	/* Transmit FIFO underrun interrupt */
#define	AR_IMR_MIB	0x00001000	/* MIB interrupt - see MIBC */
#define	AR_IMR_SWI	0x00002000	/* Software interrupt */
#define	AR_IMR_RXPHY	0x00004000	/* PHY receive error interrupt */
#define	AR_IMR_RXKCM	0x00008000	/* Key-cache miss interrupt */
#define	AR_IMR_SWBA	0x00010000	/* Software beacon alert interrupt */
#define	AR_IMR_BRSSI	0x00020000	/* Beacon threshold interrupt */
#define	AR_IMR_BMISS	0x00040000	/* Beacon missed interrupt */
#define	AR_IMR_HIUERR	0x00080000	/* An unexpected bus error has occurred */
#define	AR_IMR_BNR	0x00100000	/* BNR interrupt */
#define	AR_IMR_TIM	0x00800000	/* TIM interrupt */
#define	AR_IMR_GPIO	0x01000000	/* GPIO Interrupt */
#define	AR_IMR_QCBROVF	0x02000000	/* QCU CBR overflow interrupt */
#define	AR_IMR_QCBRURN	0x04000000	/* QCU CBR underrun interrupt */
#define	AR_IMR_QTRIG	0x08000000	/* QCU scheduling trigger interrupt */
#define	AR_IMR_RESV0	0xF0000000	/* Reserved */

#define	AR_IMR_S0_QCU_TXOK	0x000003FF	/* Mask for TXOK (QCU 0-9) */
#define	AR_IMR_S0_QCU_TXOK_S	0
#define	AR_IMR_S0_QCU_TXDESC	0x03FF0000	/* Mask for TXDESC (QCU 0-9) */
#define	AR_IMR_S0_QCU_TXDESC_S	16        	/* Shift for TXDESC (QCU 0-9) */

#define	AR_IMR_S1_QCU_TXERR	0x000003FF	/* Mask for TXERR (QCU 0-9) */
#define	AR_IMR_S1_QCU_TXERR_S	0
#define	AR_IMR_S1_QCU_TXEOL	0x03FF0000	/* Mask for TXEOL (QCU 0-9) */
#define	AR_IMR_S1_QCU_TXEOL_S	16        	/* Shift for TXEOL (QCU 0-9) */

#define	AR_IMR_S2_QCU_TXURN	0x000003FF	/* Mask for TXURN (QCU 0-9) */
#define	AR_IMR_S2_QCU_TXURN_S	0
#define	AR_IMR_S2_MCABT	0x00010000	/* Master cycle abort interrupt */
#define	AR_IMR_S2_SSERR	0x00020000	/* SERR interrupt */
#define	AR_IMR_S2_DPERR	0x00040000	/* PCI bus parity error */
#define	AR_IMR_S2_RESV0	0xFFF80000	/* Reserved */

#define	AR_IMR_S3_QCU_QCBROVF_M	0x000003FF	/* Mask for QCBROVF (QCU 0-9) */
#define	AR_IMR_S3_QCU_QCBRURN_M	0x03FF0000	/* Mask for QCBRURN (QCU 0-9) */
#define	AR_IMR_S3_QCU_QCBRURN_S	16        	/* Shift for QCBRURN (QCU 0-9) */

#define	AR_IMR_S4_QCU_QTRIG_M	0x000003FF	/* Mask for QTRIG (QCU 0-9) */
#define	AR_IMR_S4_RESV0	0xFFFFFC00	/* Reserved */

	/* Interrupt status registers (read-and-clear access, secondary shadow copies) */

	/* QCU registers */
#define	AR_NUM_QCU	10    	/* Only use QCU 0-9 for forward QCU compatibility */
#define	AR_QCU_0	0x0001
#define	AR_QCU_1	0x0002
#define	AR_QCU_2	0x0004
#define	AR_QCU_3	0x0008
#define	AR_QCU_4	0x0010
#define	AR_QCU_5	0x0020
#define	AR_QCU_6	0x0040
#define	AR_QCU_7	0x0080
#define	AR_QCU_8	0x0100
#define	AR_QCU_9	0x0200

#define	AR_Q_TXE_M	0x000003FF	/* Mask for TXE (QCU 0-9) */

#define	AR_Q_TXD_M	0x000003FF	/* Mask for TXD (QCU 0-9) */

#define	AR_Q_CBRCFG_CBR_INTERVAL	0x00FFFFFF	/* Mask for CBR interval (us) */
#define	AR_Q_CBRCFG_CBR_INTERVAL_S		0	/* Shift for CBR interval */
#define	AR_Q_CBRCFG_CBR_OVF_THRESH	0xFF000000	/* Mask for CBR overflow threshold */
#define	AR_Q_CBRCFG_CBR_OVF_THRESH_S		24	/* Shift for " " " */

#define	AR_Q_RDYTIMECFG_INT	0x00FFFFFF 	/* CBR interval (us) */
#define	AR_Q_RDYTIMECFG_INT_S	0		/* Shift for ReadyTime Interval (us) */
#define	AR_Q_RDYTIMECFG_DURATION_M	0x00FFFFFF	/* Mask for CBR interval (us) */
#define	AR_Q_RDYTIMECFG_EN	0x01000000	/* ReadyTime enable */
#define	AR_Q_RDYTIMECFG_RESV0	0xFE000000	/* Reserved */

#define	AR_Q_ONESHOTARM_SC_M	0x0000FFFF	/* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */
#define	AR_Q_ONESHOTARM_SC_RESV0 0xFFFF0000	/* Reserved */

#define	AR_Q_ONESHOTARM_CC_M	0x0000FFFF	/* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */
#define	AR_Q_ONESHOTARM_CC_RESV0 0xFFFF0000	/* Reserved */

#define	AR_Q_MISC_FSP_M		0x0000000F	/* Mask for Frame Scheduling Policy */
#define	AR_Q_MISC_FSP_ASAP		0	/* ASAP */
#define	AR_Q_MISC_FSP_CBR		1	/* CBR */
#define	AR_Q_MISC_FSP_DBA_GATED		2	/* DMA Beacon Alert gated */
#define	AR_Q_MISC_FSP_TIM_GATED		3	/* TIM gated */
#define	AR_Q_MISC_FSP_BEACON_SENT_GATED	4	/* Beacon-sent-gated */
#define	AR_Q_MISC_ONE_SHOT_EN	0x00000010	/* OneShot enable */
#define	AR_Q_MISC_CBR_INCR_DIS1	0x00000020	/* Disable CBR expired counter
						   incr (empty q) */
#define	AR_Q_MISC_CBR_INCR_DIS0	0x00000040	/* Disable CBR expired counter
						   incr (empty beacon q) */
#define	AR_Q_MISC_BEACON_USE	0x00000080	/* Beacon use indication */
#define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT	0x00000100	/* CBR expired counter limit enable */
#define	AR_Q_MISC_RDYTIME_EXP_POLICY	0x00000200	/* Enable TXE cleared on ReadyTime expired or VEOL */
#define	AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400	/* Reset CBR expired counter */
#define	AR_Q_MISC_DCU_EARLY_TERM_REQ	0x00000800	/* DCU frame early termination request control */
#define	AR_Q_MISC_RESV0	0xFFFFF000	/* Reserved */

#define	AR_Q_STS_PEND_FR_CNT_M	0x00000003	/* Mask for Pending Frame Count */
#define	AR_Q_STS_RESV0	0x000000FC	/* Reserved */
#define	AR_Q_STS_CBR_EXP_CNT_M	0x0000FF00	/* Mask for CBR expired counter */
#define	AR_Q_STS_RESV1	0xFFFF0000	/* Reserved */

#define	AR_Q_RDYTIMESHDN_M	0x000003FF	/* Mask for ReadyTimeShutdown status (QCU 0-9) */

	/* DCU registers */
#define	AR_NUM_DCU	10    	/* Only use 10 DCU's for forward QCU/DCU compatibility */
#define	AR_DCU_0	0x0001
#define	AR_DCU_1	0x0002
#define	AR_DCU_2	0x0004
#define	AR_DCU_3	0x0008
#define	AR_DCU_4	0x0010
#define	AR_DCU_5	0x0020
#define	AR_DCU_6	0x0040
#define	AR_DCU_7	0x0080
#define	AR_DCU_8	0x0100
#define	AR_DCU_9	0x0200

#define	AR_D_QCUMASK_M	0x000003FF	/* Mask for QCU Mask (QCU 0-9) */
#define	AR_D_QCUMASK_RESV0	0xFFFFFC00	/* Reserved */

#define	AR_D_LCL_IFS_CWMIN	0x000003FF	/* Mask for CW_MIN */
#define	AR_D_LCL_IFS_CWMIN_S	0		/* Shift for CW_MIN */
#define	AR_D_LCL_IFS_CWMAX	0x000FFC00	/* Mask for CW_MAX */
#define	AR_D_LCL_IFS_CWMAX_S	10        	/* Shift for CW_MAX */
#define	AR_D_LCL_IFS_AIFS	0x0FF00000	/* Mask for AIFS */
#define	AR_D_LCL_IFS_AIFS_S	20        	/* Shift for AIFS */
#define	AR_D_LCL_IFS_RESV0	0xF0000000	/* Reserved */

#define	AR_D_RETRY_LIMIT_FR_SH	0x0000000F	/* Mask for frame short retry limit */
#define	AR_D_RETRY_LIMIT_FR_SH_S	0	/* Shift for frame short retry limit */
#define	AR_D_RETRY_LIMIT_FR_LG	0x000000F0	/* Mask for frame long retry limit */
#define	AR_D_RETRY_LIMIT_FR_LG_S	4	/* Shift for frame long retry limit */
#define	AR_D_RETRY_LIMIT_STA_SH	0x00003F00	/* Mask for station short retry limit */
#define	AR_D_RETRY_LIMIT_STA_SH_S	8	/* Shift for station short retry limit */
#define	AR_D_RETRY_LIMIT_STA_LG	0x000FC000	/* Mask for station short retry limit */
#define	AR_D_RETRY_LIMIT_STA_LG_S	14	/* Shift for station short retry limit */
#define	AR_D_RETRY_LIMIT_RESV0	0xFFF00000	/* Reserved */

#define	AR_D_CHNTIME_EN	0x00100000	/* ChannelTime enable */
#define	AR_D_CHNTIME_RESV0	0xFFE00000	/* Reserved */
#define	AR_D_CHNTIME_DUR	0x000FFFFF	/* Mask for ChannelTime duration (us) */
#define AR_D_CHNTIME_DUR_S              0 /* Shift for ChannelTime duration */

#define	AR_D_MISC_BKOFF_THRESH_M	0x000007FF	/* Mask for Backoff threshold setting */
#define AR_D_MISC_FRAG_BKOFF_EN         0x00000200 /* Backoff during a frag burst */