ar5211reg.h.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

/*
 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
 * Copyright (c) 2002-2006 Atheros Communications, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 * $Id: ar5211reg.h,v 1.4 2008/11/10 01:19:38 sam Exp $
 */
#ifndef _DEV_ATH_AR5211REG_H
#define _DEV_ATH_AR5211REG_H

/*
 * Definitions for the Atheros AR5211/5311 chipset.
 */

/*
 * Maui2/Spirit specific registers/fields are indicated by AR5311.
 * Oahu specific registers/fields are indicated by AR5211.
 */

/* DMA Control and Interrupt Registers */
#define	AR_CR		0x0008		/* control register */
#define	AR_RXDP		0x000C		/* receive queue descriptor pointer */
#define	AR_CFG		0x0014		/* configuration and status register */
#define	AR_IER		0x0024		/* Interrupt enable register */
#define	AR_RTSD0	0x0028		/* RTS Duration Parameters 0 */
#define	AR_RTSD1	0x002c		/* RTS Duration Parameters 1 */
#define	AR_TXCFG	0x0030		/* tx DMA size config register */
#define	AR_RXCFG	0x0034		/* rx DMA size config register */
#define	AR5211_JUMBO_LAST	0x0038	/* Jumbo descriptor last address */
#define	AR_MIBC		0x0040		/* MIB control register */
#define	AR_TOPS		0x0044		/* timeout prescale count */
#define	AR_RXNPTO	0x0048		/* no frame received timeout */
#define	AR_TXNPTO	0x004C		/* no frame trasmitted timeout */
#define	AR_RFGTO	0x0050		/* receive frame gap timeout */
#define	AR_RFCNT	0x0054		/* receive frame count limit */
#define	AR_MACMISC	0x0058		/* miscellaneous control/status */
#define	AR5311_QDCLKGATE	0x005c	/* QCU/DCU clock gating control */
#define	AR_ISR		0x0080		/* Primary interrupt status register */
#define	AR_ISR_S0	0x0084		/* Secondary interrupt status reg 0 */
#define	AR_ISR_S1	0x0088		/* Secondary interrupt status reg 1 */
#define	AR_ISR_S2	0x008c		/* Secondary interrupt status reg 2 */
#define	AR_ISR_S3	0x0090		/* Secondary interrupt status reg 3 */
#define	AR_ISR_S4	0x0094		/* Secondary interrupt status reg 4 */
#define	AR_IMR		0x00a0		/* Primary interrupt mask register */
#define	AR_IMR_S0	0x00a4		/* Secondary interrupt mask reg 0 */
#define	AR_IMR_S1	0x00a8		/* Secondary interrupt mask reg 1 */
#define	AR_IMR_S2	0x00ac		/* Secondary interrupt mask reg 2 */
#define	AR_IMR_S3	0x00b0		/* Secondary interrupt mask reg 3 */
#define	AR_IMR_S4	0x00b4		/* Secondary interrupt mask reg 4 */
#define	AR_ISR_RAC	0x00c0		/* Primary interrupt status reg, */
/* Shadow copies with read-and-clear access */
#define	AR_ISR_S0_S	0x00c4		/* Secondary interrupt status reg 0 */
#define	AR_ISR_S1_S	0x00c8		/* Secondary interrupt status reg 1 */
#define	AR_ISR_S2_S	0x00cc		/* Secondary interrupt status reg 2 */
#define	AR_ISR_S3_S	0x00d0		/* Secondary interrupt status reg 3 */
#define	AR_ISR_S4_S	0x00d4		/* Secondary interrupt status reg 4 */

#define	AR_Q0_TXDP	0x0800		/* Transmit Queue descriptor pointer */
#define	AR_Q1_TXDP	0x0804		/* Transmit Queue descriptor pointer */
#define	AR_Q2_TXDP	0x0808		/* Transmit Queue descriptor pointer */
#define	AR_Q3_TXDP	0x080c		/* Transmit Queue descriptor pointer */
#define	AR_Q4_TXDP	0x0810		/* Transmit Queue descriptor pointer */
#define	AR_Q5_TXDP	0x0814		/* Transmit Queue descriptor pointer */
#define	AR_Q6_TXDP	0x0818		/* Transmit Queue descriptor pointer */
#define	AR_Q7_TXDP	0x081c		/* Transmit Queue descriptor pointer */
#define	AR_Q8_TXDP	0x0820		/* Transmit Queue descriptor pointer */
#define	AR_Q9_TXDP	0x0824		/* Transmit Queue descriptor pointer */
#define	AR_QTXDP(i)	(AR_Q0_TXDP + ((i)<<2))

#define	AR_Q_TXE	0x0840		/* Transmit Queue enable */
#define	AR_Q_TXD	0x0880		/* Transmit Queue disable */

#define	AR_Q0_CBRCFG	0x08c0		/* CBR configuration */
#define	AR_Q1_CBRCFG	0x08c4		/* CBR configuration */
#define	AR_Q2_CBRCFG	0x08c8		/* CBR configuration */
#define	AR_Q3_CBRCFG	0x08cc		/* CBR configuration */
#define	AR_Q4_CBRCFG	0x08d0		/* CBR configuration */
#define	AR_Q5_CBRCFG	0x08d4		/* CBR configuration */
#define	AR_Q6_CBRCFG	0x08d8		/* CBR configuration */
#define	AR_Q7_CBRCFG	0x08dc		/* CBR configuration */
#define	AR_Q8_CBRCFG	0x08e0		/* CBR configuration */
#define	AR_Q9_CBRCFG	0x08e4		/* CBR configuration */
#define	AR_QCBRCFG(i)	(AR_Q0_CBRCFG + ((i)<<2))

#define	AR_Q0_RDYTIMECFG	0x0900	/* ReadyTime configuration */
#define	AR_Q1_RDYTIMECFG	0x0904	/* ReadyTime configuration */
#define	AR_Q2_RDYTIMECFG	0x0908	/* ReadyTime configuration */
#define	AR_Q3_RDYTIMECFG	0x090c	/* ReadyTime configuration */
#define	AR_Q4_RDYTIMECFG	0x0910	/* ReadyTime configuration */
#define	AR_Q5_RDYTIMECFG	0x0914	/* ReadyTime configuration */
#define	AR_Q6_RDYTIMECFG	0x0918	/* ReadyTime configuration */
#define	AR_Q7_RDYTIMECFG	0x091c	/* ReadyTime configuration */
#define	AR_Q8_RDYTIMECFG	0x0920	/* ReadyTime configuration */
#define	AR_Q9_RDYTIMECFG	0x0924	/* ReadyTime configuration */
#define	AR_QRDYTIMECFG(i)	(AR_Q0_RDYTIMECFG + ((i)<<2))

#define	AR_Q_ONESHOTARM_SC	0x0940	/* OneShotArm set control */
#define	AR_Q_ONESHOTARM_CC	0x0980	/* OneShotArm clear control */

#define	AR_Q0_MISC	0x09c0		/* Miscellaneous QCU settings */
#define	AR_Q1_MISC	0x09c4		/* Miscellaneous QCU settings */
#define	AR_Q2_MISC	0x09c8		/* Miscellaneous QCU settings */
#define	AR_Q3_MISC	0x09cc		/* Miscellaneous QCU settings */
#define	AR_Q4_MISC	0x09d0		/* Miscellaneous QCU settings */
#define	AR_Q5_MISC	0x09d4		/* Miscellaneous QCU settings */
#define	AR_Q6_MISC	0x09d8		/* Miscellaneous QCU settings */
#define	AR_Q7_MISC	0x09dc		/* Miscellaneous QCU settings */
#define	AR_Q8_MISC	0x09e0		/* Miscellaneous QCU settings */
#define	AR_Q9_MISC	0x09e4		/* Miscellaneous QCU settings */
#define	AR_QMISC(i)	(AR_Q0_MISC + ((i)<<2))

#define	AR_Q0_STS	0x0a00		/* Miscellaneous QCU status */
#define	AR_Q1_STS	0x0a04		/* Miscellaneous QCU status */
#define	AR_Q2_STS	0x0a08		/* Miscellaneous QCU status */
#define	AR_Q3_STS	0x0a0c		/* Miscellaneous QCU status */
#define	AR_Q4_STS	0x0a10		/* Miscellaneous QCU status */
#define	AR_Q5_STS	0x0a14		/* Miscellaneous QCU status */
#define	AR_Q6_STS	0x0a18		/* Miscellaneous QCU status */
#define	AR_Q7_STS	0x0a1c		/* Miscellaneous QCU status */
#define	AR_Q8_STS	0x0a20		/* Miscellaneous QCU status */
#define	AR_Q9_STS	0x0a24		/* Miscellaneous QCU status */
#define	AR_QSTS(i)	(AR_Q0_STS + ((i)<<2))

#define	AR_Q_RDYTIMESHDN	0x0a40	/* ReadyTimeShutdown status */
#define	AR_D0_QCUMASK	0x1000		/* QCU Mask */
#define	AR_D1_QCUMASK	0x1004		/* QCU Mask */
#define	AR_D2_QCUMASK	0x1008		/* QCU Mask */
#define	AR_D3_QCUMASK	0x100c		/* QCU Mask */
#define	AR_D4_QCUMASK	0x1010		/* QCU Mask */
#define	AR_D5_QCUMASK	0x1014		/* QCU Mask */
#define	AR_D6_QCUMASK	0x1018		/* QCU Mask */
#define	AR_D7_QCUMASK	0x101c		/* QCU Mask */
#define	AR_D8_QCUMASK	0x1020		/* QCU Mask */
#define	AR_D9_QCUMASK	0x1024		/* QCU Mask */
#define	AR_DQCUMASK(i)	(AR_D0_QCUMASK + ((i)<<2))

#define	AR_D0_LCL_IFS	0x1040		/* DCU-specific IFS settings */
#define	AR_D1_LCL_IFS	0x1044		/* DCU-specific IFS settings */
#define	AR_D2_LCL_IFS	0x1048		/* DCU-specific IFS settings */
#define	AR_D3_LCL_IFS	0x104c		/* DCU-specific IFS settings */
#define	AR_D4_LCL_IFS	0x1050		/* DCU-specific IFS settings */
#define	AR_D5_LCL_IFS	0x1054		/* DCU-specific IFS settings */
#define	AR_D6_LCL_IFS	0x1058		/* DCU-specific IFS settings */
#define	AR_D7_LCL_IFS	0x105c		/* DCU-specific IFS settings */
#define	AR_D8_LCL_IFS	0x1060		/* DCU-specific IFS settings */
#define	AR_D9_LCL_IFS	0x1064		/* DCU-specific IFS settings */
#define	AR_DLCL_IFS(i)	(AR_D0_LCL_IFS + ((i)<<2))

#define	AR_D0_RETRY_LIMIT	0x1080	/* Retry limits */
#define	AR_D1_RETRY_LIMIT	0x1084	/* Retry limits */
#define	AR_D2_RETRY_LIMIT	0x1088	/* Retry limits */
#define	AR_D3_RETRY_LIMIT	0x108c	/* Retry limits */
#define	AR_D4_RETRY_LIMIT	0x1090	/* Retry limits */
#define	AR_D5_RETRY_LIMIT	0x1094	/* Retry limits */
#define	AR_D6_RETRY_LIMIT	0x1098	/* Retry limits */
#define	AR_D7_RETRY_LIMIT	0x109c	/* Retry limits */
#define	AR_D8_RETRY_LIMIT	0x10a0	/* Retry limits */
#define	AR_D9_RETRY_LIMIT	0x10a4	/* Retry limits */
#define	AR_DRETRY_LIMIT(i)	(AR_D0_RETRY_LIMIT + ((i)<<2))

#define	AR_D0_CHNTIME	0x10c0		/* ChannelTime settings */
#define	AR_D1_CHNTIME	0x10c4		/* ChannelTime settings */
#define	AR_D2_CHNTIME	0x10c8		/* ChannelTime settings */
#define	AR_D3_CHNTIME	0x10cc		/* ChannelTime settings */
#define	AR_D4_CHNTIME	0x10d0		/* ChannelTime settings */
#define	AR_D5_CHNTIME	0x10d4		/* ChannelTime settings */
#define	AR_D6_CHNTIME	0x10d8		/* ChannelTime settings */
#define	AR_D7_CHNTIME	0x10dc		/* ChannelTime settings */
#define	AR_D8_CHNTIME	0x10e0		/* ChannelTime settings */
#define	AR_D9_CHNTIME	0x10e4		/* ChannelTime settings */
#define	AR_DCHNTIME(i)	(AR_D0_CHNTIME + ((i)<<2))

#define	AR_D0_MISC	0x1100		/* Misc DCU-specific settings */
#define	AR_D1_MISC	0x1104		/* Misc DCU-specific settings */
#define	AR_D2_MISC	0x1108		/* Misc DCU-specific settings */
#define	AR_D3_MISC	0x110c		/* Misc DCU-specific settings */
#define	AR_D4_MISC	0x1110		/* Misc DCU-specific settings */
#define	AR_D5_MISC	0x1114		/* Misc DCU-specific settings */
#define	AR_D6_MISC	0x1118		/* Misc DCU-specific settings */
#define	AR_D7_MISC	0x111c		/* Misc DCU-specific settings */
#define	AR_D8_MISC	0x1120		/* Misc DCU-specific settings */
#define	AR_D9_MISC	0x1124		/* Misc DCU-specific settings */
#define	AR_DMISC(i)	(AR_D0_MISC + ((i)<<2))

#define	AR_D0_SEQNUM	0x1140		/* Frame seqnum control/status */
#define	AR_D1_SEQNUM	0x1144		/* Frame seqnum control/status */
#define	AR_D2_SEQNUM	0x1148		/* Frame seqnum control/status */
#define	AR_D3_SEQNUM	0x114c		/* Frame seqnum control/status */
#define	AR_D4_SEQNUM	0x1150		/* Frame seqnum control/status */
#define	AR_D5_SEQNUM	0x1154		/* Frame seqnum control/status */
#define	AR_D6_SEQNUM	0x1158		/* Frame seqnum control/status */
#define	AR_D7_SEQNUM	0x115c		/* Frame seqnum control/status */
#define	AR_D8_SEQNUM	0x1160		/* Frame seqnum control/status */
#define	AR_D9_SEQNUM	0x1164		/* Frame seqnum control/status */
#define	AR_DSEQNUM(i)	(AR_D0_SEQNUM + ((i<<2)))

/* MAC DCU-global IFS settings */
#define	AR_D_GBL_IFS_SIFS	0x1030	/* DCU global SIFS settings */
#define	AR_D_GBL_IFS_SLOT	0x1070	/* DC global slot interval */
#define	AR_D_GBL_IFS_EIFS	0x10b0	/* DCU global EIFS setting */
#define	AR_D_GBL_IFS_MISC	0x10f0	/* DCU global misc. IFS settings */
#define	AR_D_FPCTL	0x1230		/* DCU frame prefetch settings */
#define	AR_D_TXPSE	0x1270		/* DCU transmit pause control/status */
#define	AR_D_TXBLK_CMD	0x1038		/* DCU transmit filter cmd (w/only) */
#define	AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))	/* DCU transmit filter data */
#define	AR_D_TXBLK_CLR	0x143c		/* DCU clear tx filter (w/only) */
#define	AR_D_TXBLK_SET	0x147c		/* DCU set tx filter (w/only) */

#define	AR_D_TXPSE	0x1270		/* DCU transmit pause control/status */

#define	AR_RC		0x4000		/* Warm reset control register */
#define	AR_SCR		0x4004		/* Sleep control register */
#define	AR_INTPEND	0x4008		/* Interrupt Pending register */
#define	AR_SFR		0x400C		/* Sleep force register */
#define	AR_PCICFG	0x4010		/* PCI configuration register */
#define	AR_GPIOCR	0x4014		/* GPIO control register */
#define	AR_GPIODO	0x4018		/* GPIO data output access register */
#define	AR_GPIODI	0x401C		/* GPIO data input access register */
#define	AR_SREV		0x4020		/* Silicon Revision register */

#define	AR_EEPROM_ADDR	0x6000		/* EEPROM address register (10 bit) */
#define	AR_EEPROM_DATA	0x6004		/* EEPROM data register (16 bit) */
#define	AR_EEPROM_CMD	0x6008		/* EEPROM command register */
#define	AR_EEPROM_STS	0x600c		/* EEPROM status register */
#define	AR_EEPROM_CFG	0x6010		/* EEPROM configuration register */

#define	AR_STA_ID0	0x8000		/* station ID0 - low 32 bits */
#define	AR_STA_ID1	0x8004		/* station ID1 - upper 16 bits */
#define	AR_BSS_ID0	0x8008		/* BSSID low 32 bits */
#define	AR_BSS_ID1	0x800C		/* BSSID upper 16 bits / AID */
#define	AR_SLOT_TIME	0x8010		/* Time-out after a collision */
#define	AR_TIME_OUT	0x8014		/* ACK & CTS time-out */
#define	AR_RSSI_THR	0x8018		/* RSSI warning & missed beacon threshold */
#define	AR_USEC		0x801c		/* transmit latency register */
#define	AR_BEACON	0x8020		/* beacon control value/mode bits */
#define	AR_CFP_PERIOD	0x8024		/* CFP Interval (TU/msec) */
#define	AR_TIMER0	0x8028		/* Next beacon time (TU/msec) */
#define	AR_TIMER1	0x802c		/* DMA beacon alert time (1/8 TU) */
#define	AR_TIMER2	0x8030		/* Software beacon alert (1/8 TU) */
#define	AR_TIMER3	0x8034		/* ATIM window time */
#define	AR_CFP_DUR	0x8038		/* maximum CFP duration in TU */
#define	AR_RX_FILTER	0x803C		/* receive filter register */
#define	AR_MCAST_FIL0	0x8040		/* multicast filter lower 32 bits */
#define	AR_MCAST_FIL1	0x8044		/* multicast filter upper 32 bits */
#define	AR_DIAG_SW	0x8048		/* PCU control register */
#define	AR_TSF_L32	0x804c		/* local clock lower 32 bits */
#define	AR_TSF_U32	0x8050		/* local clock upper 32 bits */
#define	AR_TST_ADDAC	0x8054		/* ADDAC test register */
#define	AR_DEF_ANTENNA	0x8058		/* default antenna register */

#define	AR_LAST_TSTP	0x8080		/* Time stamp of the last beacon rcvd */
#define	AR_NAV		0x8084		/* current NAV value */
#define	AR_RTS_OK	0x8088		/* RTS exchange success counter */
#define	AR_RTS_FAIL	0x808c		/* RTS exchange failure counter */
#define	AR_ACK_FAIL	0x8090		/* ACK failure counter */
#define	AR_FCS_FAIL	0x8094		/* FCS check failure counter */
#define	AR_BEACON_CNT	0x8098		/* Valid beacon counter */

#define	AR_KEYTABLE_0	0x8800		/* Encryption key table */
#define	AR_KEYTABLE(n)	(AR_KEYTABLE_0 + ((n)*32))

#define	AR_CR_RXE	0x00000004	/* Receive enable */
#define	AR_CR_RXD	0x00000020	/* Receive disable */
#define	AR_CR_SWI	0x00000040	/* One-shot software interrupt */
#define	AR_CR_BITS	"\20\3RXE\6RXD\7SWI"

#define	AR_CFG_SWTD	0x00000001	/* byteswap tx descriptor words */
#define	AR_CFG_SWTB	0x00000002	/* byteswap tx data buffer words */
#define	AR_CFG_SWRD	0x00000004	/* byteswap rx descriptor words */
#define	AR_CFG_SWRB	0x00000008	/* byteswap rx data buffer words */
#define	AR_CFG_SWRG	0x00000010	/* byteswap register access data words */
#define	AR_CFG_AP_ADHOC_INDICATION	0x00000020	/* AP/adhoc indication (0-AP, 1-Adhoc) */
#define	AR_CFG_PHOK	0x00000100	/* PHY OK status */
#define	AR_CFG_EEBS	0x00000200	/* EEPROM busy */