ar5212_reset.c

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

	int16_t nf, nfThresh;
 	int32_t val;

	if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
		HALDEBUG(ah, HAL_DEBUG_ANY,
		    "%s: NF did not complete in calibration window\n", __func__);
		chan->rawNoiseFloor = h->privNF;	/* most recent value */
		return chan->rawNoiseFloor;
	}

	/*
	 * Finished NF cal, check against threshold.
	 */
	nf = ar5212GetNoiseFloor(ah);
	if (getNoiseFloorThresh(ah, chan, &nfThresh)) {
		if (nf > nfThresh) {
			HALDEBUG(ah, HAL_DEBUG_ANY,
			    "%s: noise floor failed detected; detected %u, "
			    "threshold %u\n", __func__, nf, nfThresh);
			/*
			 * NB: Don't discriminate 2.4 vs 5Ghz, if this
			 *     happens it indicates a problem regardless
			 *     of the band.
			 */
			chan->channelFlags |= CHANNEL_CW_INT;
			nf = 0;
		}
	} else
		nf = 0;

	/*
	 * Pass through histogram and write median value as
	 * calculated from the accrued window.  We require a
	 * full window of in-range values to be seen before we
	 * start using the history.
	 */
	updateNFHistBuff(h, nf);
	if (h->first_run) {
		if (nf < AR5212_CCA_MIN_BAD_VALUE ||
		    nf > AR5212_CCA_MAX_HIGH_VALUE) {
			nf = AR5212_CCA_MAX_GOOD_VALUE;
			h->invalidNFcount = AR512_NF_CAL_HIST_MAX;
		} else if (--(h->invalidNFcount) == 0) {
			h->first_run = 0;
			h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer);
		} else {
			nf = AR5212_CCA_MAX_GOOD_VALUE;
		}
	} else {
		h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer);
	}

	val = OS_REG_READ(ah, AR_PHY(25));
	val &= 0xFFFFFE00;
	val |= (((uint32_t)nf << 1) & 0x1FF);
	OS_REG_WRITE(ah, AR_PHY(25), val);
	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) {
#ifdef AH_DEBUG
		ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n",
		    __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
#endif
	}

	/*
	 * Now load a high maxCCAPower value again so that we're
	 * not capped by the median we just loaded
	 */
	val &= 0xFFFFFE00;
	val |= (((uint32_t)(-50) << 1) & 0x1FF);
	OS_REG_WRITE(ah, AR_PHY(25), val);
	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);

	return (chan->rawNoiseFloor = nf);
}

/*
 * Set up compression configuration registers
 */
void
ar5212SetCompRegs(struct ath_hal *ah)
{
	struct ath_hal_5212 *ahp = AH5212(ah);
	int i;

        /* Check if h/w supports compression */
	if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport)
		return;

	OS_REG_WRITE(ah, AR_DCCFG, 1);

	OS_REG_WRITE(ah, AR_CCFG,
		(AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M);

	OS_REG_WRITE(ah, AR_CCFG,
		OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN);
	OS_REG_WRITE(ah, AR_CCUCFG,
		AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN);

	OS_REG_WRITE(ah, AR_CPCOVF, 0);

	/* reset decompression mask */
	for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) {
		OS_REG_WRITE(ah, AR_DCM_A, i);
		OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]);
	}
}

HAL_BOOL
ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
	const HAL_CHANNEL_INTERNAL *chan)
{
#define	ANT_SWITCH_TABLE1	AR_PHY(88)
#define	ANT_SWITCH_TABLE2	AR_PHY(89)
	struct ath_hal_5212 *ahp = AH5212(ah);
	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
	uint32_t antSwitchA, antSwitchB;
	int ix;
	HAL_BOOL isBmode = AH_FALSE;
	/* NB: need local copy for SAVE/RESTORE 'cuz chan is const */
	HAL_CHANNEL_INTERNAL ichan = *chan;

	HALASSERT(ah->ah_magic == AR5212_MAGIC);
	HALASSERT(ahp->ah_phyPowerOn);

	SAVE_CCK(ah, &ichan, isBmode);
	switch (ichan.channelFlags & CHANNEL_ALL_NOTURBO) {
	case CHANNEL_A:		ix = 0; break;
	case CHANNEL_B:		ix = 1; break;
	case CHANNEL_PUREG:	ix = 2; break;
	default:
		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
		    __func__, ichan.channelFlags);
		RESTORE_CCK(ah, &ichan, isBmode);
		return AH_FALSE;
	}
	RESTORE_CCK(ah, &ichan, isBmode);

	antSwitchA =  ee->ee_antennaControl[1][ix]
		   | (ee->ee_antennaControl[2][ix] << 6)
		   | (ee->ee_antennaControl[3][ix] << 12) 
		   | (ee->ee_antennaControl[4][ix] << 18)
		   | (ee->ee_antennaControl[5][ix] << 24)
		   ;
	antSwitchB =  ee->ee_antennaControl[6][ix]
		   | (ee->ee_antennaControl[7][ix] << 6)
		   | (ee->ee_antennaControl[8][ix] << 12)
		   | (ee->ee_antennaControl[9][ix] << 18)
		   | (ee->ee_antennaControl[10][ix] << 24)
		   ;
	/*
	 * For fixed antenna, give the same setting for both switch banks
	 */
	switch (settings) {
	case HAL_ANT_FIXED_A:
		antSwitchB = antSwitchA;
		break;
	case HAL_ANT_FIXED_B:
		antSwitchA = antSwitchB;
		break;
	case HAL_ANT_VARIABLE:
		break;
	default:
		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",
		    __func__, settings);
		return AH_FALSE;
	}
	if (antSwitchB == antSwitchA) {
		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
		    "%s: Setting fast diversity off.\n", __func__);
		OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 
			       AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
		ahp->ah_diversity = AH_FALSE;
	} else {
		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
		    "%s: Setting fast diversity on.\n", __func__);
		OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 
			       AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
		ahp->ah_diversity = AH_TRUE;
	}
	ahp->ah_antControl = settings;

	OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);
	OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);

	return AH_TRUE;
#undef ANT_SWITCH_TABLE2
#undef ANT_SWITCH_TABLE1
}

HAL_BOOL
ar5212IsSpurChannel(struct ath_hal *ah, HAL_CHANNEL *chan)
{
    uint32_t clockFreq =
	((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32);
    return ( ((chan->channel % clockFreq) != 0)
          && (((chan->channel % clockFreq) < 10)
         || (((chan->channel) % clockFreq) > 22)) );
}

/*
 * Read EEPROM header info and program the device for correct operation
 * given the channel value.
 */
HAL_BOOL
ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
{
#define NO_FALSE_DETECT_BACKOFF   2
#define CB22_FALSE_DETECT_BACKOFF 6
#define	AR_PHY_BIS(_ah, _reg, _mask, _val) \
	OS_REG_WRITE(_ah, AR_PHY(_reg), \
		(OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val));
	struct ath_hal_5212 *ahp = AH5212(ah);
	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
	int arrayMode, falseDectectBackoff;
	int is2GHz = IS_CHAN_2GHZ(chan);
	int8_t adcDesiredSize, pgaDesiredSize;
	uint16_t switchSettling, txrxAtten, rxtxMargin;
	int iCoff, qCoff;

	HALASSERT(ah->ah_magic == AR5212_MAGIC);

	switch (chan->channelFlags & CHANNEL_ALL) {
	case CHANNEL_A:
	case CHANNEL_T:
		arrayMode = headerInfo11A;
		if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah))
			OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
				AR_PHY_FRAME_CTL_TX_CLIP,
				ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]);
		break;
	case CHANNEL_B:
		arrayMode = headerInfo11B;
		break;
	case CHANNEL_G:
	case CHANNEL_108G:
		arrayMode = headerInfo11G;
		break;
	default:
		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
		    __func__, chan->channelFlags);
		return AH_FALSE;
	}

	/* Set the antenna register(s) correctly for the chip revision */
	AR_PHY_BIS(ah, 68, 0xFFFFFC06,
		(ee->ee_antennaControl[0][arrayMode] << 4) | 0x1);

	ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan);

	/* Set the Noise Floor Thresh on ar5211 devices */
	OS_REG_WRITE(ah, AR_PHY(90),
		(ee->ee_noiseFloorThresh[arrayMode] & 0x1FF)
		| (1 << 9));

	if (ee->ee_version >= AR_EEPROM_VER5_0 && IS_CHAN_TURBO(chan)) {
		switchSettling = ee->ee_switchSettlingTurbo[is2GHz];
		adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz];
		pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz];
		txrxAtten = ee->ee_txrxAttenTurbo[is2GHz];
		rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz];
	} else {
		switchSettling = ee->ee_switchSettling[arrayMode];
		adcDesiredSize = ee->ee_adcDesiredSize[arrayMode];
		pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz];
		txrxAtten = ee->ee_txrxAtten[is2GHz];
		rxtxMargin = ee->ee_rxtxMargin[is2GHz];
	}

	OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 
			 AR_PHY_SETTLING_SWITCH, switchSettling);
	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
			 AR_PHY_DESIRED_SZ_ADC, adcDesiredSize);
	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
			 AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize);
	OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
			 AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten);
	OS_REG_WRITE(ah, AR_PHY(13),
		(ee->ee_txEndToXPAOff[arrayMode] << 24)
		| (ee->ee_txEndToXPAOff[arrayMode] << 16)
		| (ee->ee_txFrameToXPAOn[arrayMode] << 8)
		| ee->ee_txFrameToXPAOn[arrayMode]);
	AR_PHY_BIS(ah, 10, 0xFFFF00FF,
		ee->ee_txEndToXLNAOn[arrayMode] << 8);
	AR_PHY_BIS(ah, 25, 0xFFF80FFF,
		(ee->ee_thresh62[arrayMode] << 12) & 0x7F000);

	/*
	 * False detect backoff - suspected 32 MHz spur causes false
	 * detects in OFDM, causing Tx Hangs.  Decrease weak signal
	 * sensitivity for this card.
	 */
	falseDectectBackoff = NO_FALSE_DETECT_BACKOFF;
	if (ee->ee_version < AR_EEPROM_VER3_3) {
		/* XXX magic number */
		if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
		    IS_CHAN_OFDM(chan))
			falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
	} else {
		if (ar5212IsSpurChannel(ah, (HAL_CHANNEL *)chan)) {
			falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
		}
	}
	AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE);

	if (chan->iqCalValid) {
		iCoff = chan->iCoff;
		qCoff = chan->qCoff;
	} else {
		iCoff = ee->ee_iqCalI[is2GHz];
		qCoff = ee->ee_iqCalQ[is2GHz];
	}

	/* write previous IQ results */
	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
		AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff);
	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
		AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff);
	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
		AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);

	if (ee->ee_version >= AR_EEPROM_VER4_1) {
		if (!IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0)
			OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
				AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin);
	}
	if (ee->ee_version >= AR_EEPROM_VER5_1) {
		/* for now always disabled */
		OS_REG_WRITE(ah,  AR_PHY_HEAVY_CLIP_ENABLE,  0);
	}

	return AH_TRUE;
#undef AR_PHY_BIS
#undef NO_FALSE_DETECT_BACKOFF
#undef CB22_FALSE_DETECT_BACKOFF
}

/*
 * Apply Spur Immunity to Boards that require it.
 * Applies only to OFDM RX operation.
 */

void
ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
{
	uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0};
	uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan;
	int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset;
	int16_t numBinOffsets;
	static const uint16_t magMapFor4[4] = {1, 2, 2, 1};
	static const uint16_t magMapFor3[3] = {1, 2, 1};
	const uint16_t *pMagMap;
	HAL_BOOL is2GHz = IS_CHAN_2GHZ(ichan);
	uint32_t val;

#define CHAN_TO_SPUR(_f, _freq)   ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 )
	if (IS_2417(ah)) {
		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n",
		    __func__);
		return;
	}

	curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel);

	if (ichan->mainSpur) {
		/* Pull out the saved spur value */
		finalSpur = ichan->mainSpur;
	} else {
		/*
		 * Check if spur immunity should be performed for this channel
		 * Should only be performed once per channel and then saved
		 */
		finalSpur = AR_NO_SPUR;
		spurDetectWidth = HAL_SPUR_CHAN_WIDTH;
		if (IS_CHAN_TURBO(ichan))
			spurDetectWidth *= 2;

		/* Decide if any spur affects the current channel */
		for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
			spurChan = ath_hal_getSpurChan(ah, i, is2GHz);
			if (spurChan == AR_NO_SPUR) {
				break;
			}
			if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) &&
			    (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) {
				finalSpur = spurChan & HAL_SPUR_VAL_MASK;
				break;
			}
		}
		/* Save detected spur (or no spur) for this channel */
		ichan->mainSpur = finalSpur;
	}

	/* Write spur immunity data */
	if (finalSpur == AR_NO_SPUR) {
		/* Disable Spur Immunity Regs if they appear set */
		if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) {
			/* Clear Spur Delta Phase, Spur Freq, and enable bits */
			OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0);
			val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);
			val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
				 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
				 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
			OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val);
			OS_REG_WRITE(ah, AR_PHY_TIMING11, 0);

			/* Clear pilot masks */
			OS_REG_WRITE(ah, AR_PHY_TIMING7, 0);
			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0);
			OS_REG_WRITE(ah, AR_PHY_TIMING9, 0);
			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0);

			/* Clear magnitude masks */
			OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0);
			OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0);
			OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0);
			OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0);