ar5212reg.h

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#define	AR_GPIOCR_INT_ENA	0x00008000 /* Enable GPIO Interrupt */
#define	AR_GPIOCR_INT_SELL	0x00000000 /* Generate int if pin is low */
#define	AR_GPIOCR_INT_SELH	0x00010000 /* Generate int if pin is high */
#define	AR_GPIOCR_INT_SEL	AR_GPIOCR_INT_SELH

#define	AR_SREV_ID		0x000000FF /* Mask to read SREV info */
#define	AR_SREV_ID_S		4	   /* Mask to shift Major Rev Info */
#define	AR_SREV_REVISION	0x0000000F /* Mask for Chip revision level */
#define	AR_SREV_REVISION_MIN	0	   /* lowest revision level */
#define	AR_SREV_REVISION_MAX	0xF	   /* highest revision level */
#define	AR_SREV_FPGA		1
#define	AR_SREV_D2PLUS		2
#define	AR_SREV_D2PLUS_MS	3	/* metal spin */
#define	AR_SREV_CRETE		4
#define	AR_SREV_CRETE_MS	5	/* FCS metal spin */
#define	AR_SREV_CRETE_MS23	7	/* 2.3 metal spin (6 skipped) */
#define	AR_SREV_CRETE_23	8	/* 2.3 full tape out */
#define	AR_SREV_GRIFFIN_LITE	8
#define	AR_SREV_HAINAN		9
#define	AR_SREV_CONDOR		11
#define	AR_SREV_VERSION	0x000000F0 /* Mask for Chip version */
#define	AR_SREV_VERSION_CRETE	0
#define	AR_SREV_VERSION_MAUI_1	1
#define	AR_SREV_VERSION_MAUI_2	2
#define	AR_SREV_VERSION_SPIRIT	3
#define	AR_SREV_VERSION_OAHU	4
#define	AR_SREV_VERSION_VENICE	5
#define	AR_SREV_VERSION_GRIFFIN	7
#define	AR_SREV_VERSION_CONDOR	9
#define	AR_SREV_VERSION_EAGLE	10
#define	AR_SREV_VERSION_COBRA	11	
#define	AR_SREV_2413		AR_SREV_VERSION_GRIFFIN
#define	AR_SREV_5413	        AR_SREV_VERSION_EAGLE
#define	AR_SREV_2415		AR_SREV_VERSION_COBRA
#define	AR_SREV_5424		AR_SREV_VERSION_CONDOR
#define	AR_SREV_2425		14	/* SWAN */
#define	AR_SREV_2417		15	/* Nala */
#define	AR_SREV_OAHU_ES		0	/* Engineering Sample */
#define	AR_SREV_OAHU_PROD	2	/* Production */

#define	AR_PHYREV_HAINAN	0x43
#define	AR_ANALOG5REV_HAINAN	0x46

#define	AR_RADIO_SREV_MAJOR	0xF0
#define	AR_RADIO_SREV_MINOR	0x0F
#define	AR_RAD5111_SREV_MAJOR	0x10	/* All current supported ar5211 5 GHz
					   radios are rev 0x10 */
#define	AR_RAD5111_SREV_PROD	0x15	/* Current production level radios */
#define	AR_RAD2111_SREV_MAJOR	0x20	/* All current supported ar5211 2 GHz
					   radios are rev 0x10 */
#define	AR_RAD5112_SREV_MAJOR	0x30	/* 5112 Major Rev */
#define AR_RAD5112_SREV_2_0     0x35    /* AR5112 Revision 2.0 */
#define AR_RAD5112_SREV_2_1     0x36    /* AR5112 Revision 2.1 */
#define	AR_RAD2112_SREV_MAJOR	0x40	/* 2112 Major Rev */
#define AR_RAD2112_SREV_2_0     0x45    /* AR2112 Revision 2.0 */
#define AR_RAD2112_SREV_2_1     0x46    /* AR2112 Revision 2.1 */
#define AR_RAD2413_SREV_MAJOR	0x50	/* 2413 Major Rev */
#define AR_RAD5413_SREV_MAJOR   0x60    /* 5413 Major Rev */
#define AR_RAD2316_SREV_MAJOR	0x70	/* 2316 Major Rev */
#define AR_RAD2317_SREV_MAJOR	0x80	/* 2317 Major Rev */
#define AR_RAD5424_SREV_MAJOR   0xa0    /* Mostly same as 5413 Major Rev */

#define	AR_PCIE_PMC_ENA_L1	0x01	/* enable PCIe core enter L1 when
					   d2_sleep_en is asserted */
#define	AR_PCIE_PMC_ENA_RESET	0x08	/* enable reset on link going down */

/* EEPROM Registers in the MAC */
#define	AR_EEPROM_CMD_READ	0x00000001
#define	AR_EEPROM_CMD_WRITE	0x00000002
#define	AR_EEPROM_CMD_RESET	0x00000004

#define	AR_EEPROM_STS_READ_ERROR	0x00000001
#define	AR_EEPROM_STS_READ_COMPLETE	0x00000002
#define	AR_EEPROM_STS_WRITE_ERROR	0x00000004
#define	AR_EEPROM_STS_WRITE_COMPLETE	0x00000008

#define	AR_EEPROM_CFG_SIZE	0x00000003	/* size determination override */
#define	AR_EEPROM_CFG_SIZE_AUTO		0
#define	AR_EEPROM_CFG_SIZE_4KBIT	1
#define	AR_EEPROM_CFG_SIZE_8KBIT	2
#define	AR_EEPROM_CFG_SIZE_16KBIT	3
#define	AR_EEPROM_CFG_DIS_WWRCL	0x00000004	/* Disable wait for write completion */
#define	AR_EEPROM_CFG_CLOCK	0x00000018	/* clock rate control */
#define	AR_EEPROM_CFG_CLOCK_S		3	/* clock rate control */
#define	AR_EEPROM_CFG_CLOCK_156KHZ	0
#define	AR_EEPROM_CFG_CLOCK_312KHZ	1
#define	AR_EEPROM_CFG_CLOCK_625KHZ	2
#define	AR_EEPROM_CFG_RESV0	0x000000E0	/* Reserved */
#define	AR_EEPROM_CFG_PKEY	0x00FFFF00	/* protection key */
#define	AR_EEPROM_CFG_PKEY_S	8
#define	AR_EEPROM_CFG_EN_L	0x01000000	/* EPRM_EN_L setting */

/* MAC PCU Registers */

#define	AR_STA_ID1_SADH_MASK	0x0000FFFF /* upper 16 bits of MAC addr */
#define	AR_STA_ID1_STA_AP	0x00010000 /* Device is AP */
#define	AR_STA_ID1_ADHOC	0x00020000 /* Device is ad-hoc */
#define	AR_STA_ID1_PWR_SAV	0x00040000 /* Power save reporting in
					      self-generated frames */
#define	AR_STA_ID1_KSRCHDIS	0x00080000 /* Key search disable */
#define	AR_STA_ID1_PCF		0x00100000 /* Observe PCF */
#define	AR_STA_ID1_USE_DEFANT	0x00200000 /* Use default antenna */
#define	AR_STA_ID1_UPD_DEFANT	0x00400000 /* Update default antenna w/
					      TX antenna */
#define	AR_STA_ID1_RTS_USE_DEF	0x00800000 /* Use default antenna to send RTS */
#define	AR_STA_ID1_ACKCTS_6MB	0x01000000 /* Use 6Mb/s rate for ACK & CTS */
#define	AR_STA_ID1_BASE_RATE_11B 0x02000000/* Use 11b base rate for ACK & CTS */
#define	AR_STA_ID1_USE_DA_SG	0x04000000 /* Use default antenna for
					      self-generated frames */
#define	AR_STA_ID1_CRPT_MIC_ENABLE	0x08000000 /* Enable Michael */
#define	AR_STA_ID1_KSRCH_MODE	0x10000000 /* Look-up key when keyID != 0 */
#define	AR_STA_ID1_PRE_SEQNUM	0x20000000 /* Preserve s/w sequence number */
#define	AR_STA_ID1_CBCIV_ENDIAN	0x40000000
#define	AR_STA_ID1_MCAST_KSRCH	0x80000000 /* Do keycache search for mcast */

#define	AR_BSS_ID1_U16		0x0000FFFF /* Upper 16 bits of BSSID */
#define	AR_BSS_ID1_AID		0xFFFF0000 /* Association ID */
#define	AR_BSS_ID1_AID_S	16

#define	AR_SLOT_TIME_MASK	0x000007FF /* Slot time mask */

#define	AR_TIME_OUT_ACK		0x00003FFF /* ACK time-out */
#define	AR_TIME_OUT_ACK_S	0
#define	AR_TIME_OUT_CTS		0x3FFF0000 /* CTS time-out */
#define	AR_TIME_OUT_CTS_S	16

#define	AR_RSSI_THR_MASK	0x000000FF /* Beacon RSSI warning threshold */
#define	AR_RSSI_THR_BM_THR	0x0000FF00 /* Missed beacon threshold */
#define	AR_RSSI_THR_BM_THR_S	8

#define	AR_USEC_USEC		0x0000007F /* clock cycles in 1 usec */
#define	AR_USEC_USEC_S		0
#define	AR_USEC_USEC32		0x00003F80 /* 32MHz clock cycles in 1 usec */
#define	AR_USEC_USEC32_S	7

#define AR5212_USEC_TX_LAT_M    0x007FC000      /* Tx latency */
#define AR5212_USEC_TX_LAT_S    14
#define AR5212_USEC_RX_LAT_M    0x1F800000      /* Rx latency */
#define AR5212_USEC_RX_LAT_S    23

#define	AR_BEACON_PERIOD	0x0000FFFF /* Beacon period mask in TU/msec */
#define	AR_BEACON_PERIOD_S	0
#define	AR_BEACON_TIM		0x007F0000 /* byte offset of TIM start */
#define	AR_BEACON_TIM_S		16
#define	AR_BEACON_EN		0x00800000 /* Beacon enable */
#define	AR_BEACON_RESET_TSF	0x01000000 /* Clear TSF to 0 */

#define	AR_RX_NONE		0x00000000 /* Disallow all frames */
#define	AR_RX_UCAST		0x00000001 /* Allow unicast frames */
#define	AR_RX_MCAST		0x00000002 /* Allow multicast frames */
#define	AR_RX_BCAST		0x00000004 /* Allow broadcast frames */
#define	AR_RX_CONTROL		0x00000008 /* Allow control frames */
#define	AR_RX_BEACON		0x00000010 /* Allow beacon frames */
#define	AR_RX_PROM		0x00000020 /* Promiscuous mode, all packets */
#define	AR_RX_PROBE_REQ		0x00000080 /* Allow probe request frames */

#define	AR_DIAG_CACHE_ACK	0x00000001 /* No ACK if no valid key found */
#define	AR_DIAG_ACK_DIS		0x00000002 /* Disable ACK generation */
#define	AR_DIAG_CTS_DIS		0x00000004 /* Disable CTS generation */
#define	AR_DIAG_ENCRYPT_DIS	0x00000008 /* Disable encryption */
#define	AR_DIAG_DECRYPT_DIS	0x00000010 /* Disable decryption */
#define	AR_DIAG_RX_DIS		0x00000020 /* Disable receive */
#define	AR_DIAG_CORR_FCS	0x00000080 /* Corrupt FCS */
#define	AR_DIAG_CHAN_INFO	0x00000100 /* Dump channel info */
#define	AR_DIAG_EN_SCRAMSD	0x00000200 /* Enable fixed scrambler seed */
#define	AR_DIAG_SCRAM_SEED	0x0001FC00 /* Fixed scrambler seed */
#define	AR_DIAG_SCRAM_SEED_S	10
#define	AR_DIAG_FRAME_NV0	0x00020000 /* Accept frames of non-zero
					      protocol version */
#define	AR_DIAG_OBS_PT_SEL	0x000C0000 /* Observation point select */
#define	AR_DIAG_OBS_PT_SEL_S	18
#define AR_DIAG_RX_CLR_HI	0x00100000 /* Force rx_clear high */
#define AR_DIAG_IGNORE_CS	0x00200000 /* Force virtual carrier sense */
#define AR_DIAG_CHAN_IDLE	0x00400000 /* Force channel idle high */
#define AR_DIAG_PHEAR_ME	0x00800000 /* Uses framed and wait_wep in the pherr_enable_eifs if set to 0 */

#define	AR_SLEEP1_NEXT_DTIM	0x0007ffff /* Abs. time(1/8TU) for next DTIM */
#define	AR_SLEEP1_NEXT_DTIM_S	0
#define	AR_SLEEP1_ASSUME_DTIM	0x00080000 /* Assume DTIM present on missent beacon */
#define	AR_SLEEP1_ENH_SLEEP_ENA	0x00100000 /* Enable enhanced sleep logic */
#define	AR_SLEEP1_CAB_TIMEOUT	0xff000000 /* CAB timeout(TU) */
#define	AR_SLEEP1_CAB_TIMEOUT_S	24

#define	AR_SLEEP2_NEXT_TIM	0x0007ffff /* Abs. time(1/8TU) for next DTIM */
#define	AR_SLEEP2_NEXT_TIM_S	0
#define	AR_SLEEP2_BEACON_TIMEOUT	0xff000000 /* Beacon timeout(TU) */
#define	AR_SLEEP2_BEACON_TIMEOUT_S	24

#define	AR_SLEEP3_TIM_PERIOD	0x0000ffff /* Tim/Beacon period (TU) */
#define	AR_SLEEP3_TIM_PERIOD_S	0
#define	AR_SLEEP3_DTIM_PERIOD	0xffff0000 /* DTIM period (TU) */
#define	AR_SLEEP3_DTIM_PERIOD_S	16

#define	AR_TPC_ACK		0x0000003f /* ack frames */
#define	AR_TPC_ACK_S		0
#define	AR_TPC_CTS		0x00003f00 /* cts frames */
#define	AR_TPC_CTS_S		8
#define	AR_TPC_CHIRP		0x003f0000 /* chirp frames */
#define	AR_TPC_CHIRP_S		16
#define AR_TPC_DOPPLER          0x0f000000 /* doppler chirp span */
#define AR_TPC_DOPPLER_S        24

#define	AR_PHY_ERR_RADAR	0x00000020	/* Radar signal */
#define	AR_PHY_ERR_OFDM_TIMING	0x00020000	/* False detect for OFDM */
#define	AR_PHY_ERR_CCK_TIMING	0x02000000	/* False detect for CCK */

#define	AR_TSF_PARM_INCREMENT	0x000000ff
#define	AR_TSF_PARM_INCREMENT_S	0

#define AR_NOACK_2BIT_VALUE    0x0000000f
#define AR_NOACK_2BIT_VALUE_S  0
#define AR_NOACK_BIT_OFFSET     0x00000070
#define AR_NOACK_BIT_OFFSET_S   4
#define AR_NOACK_BYTE_OFFSET    0x00000180
#define AR_NOACK_BYTE_OFFSET_S  7

#define	AR_MISC_MODE_BSSID_MATCH_FORCE  0x1	/* Force BSSID match */
#define	AR_MISC_MODE_ACKSIFS_MEMORY     0x2	/* ACKSIFS use contents of Rate */
#define	AR_MISC_MODE_MIC_NEW_LOC_ENABLE 0x4	/* Xmit Michael Key same as Rcv */
#define	AR_MISC_MODE_TX_ADD_TSF         0x8	/* Beacon/Probe-Rsp timestamp add (not replace) */

#define	AR_KEYTABLE_KEY0(_n)	(AR_KEYTABLE(_n) + 0)	/* key bit 0-31 */
#define	AR_KEYTABLE_KEY1(_n)	(AR_KEYTABLE(_n) + 4)	/* key bit 32-47 */
#define	AR_KEYTABLE_KEY2(_n)	(AR_KEYTABLE(_n) + 8)	/* key bit 48-79 */
#define	AR_KEYTABLE_KEY3(_n)	(AR_KEYTABLE(_n) + 12)	/* key bit 80-95 */
#define	AR_KEYTABLE_KEY4(_n)	(AR_KEYTABLE(_n) + 16)	/* key bit 96-127 */
#define	AR_KEYTABLE_TYPE(_n)	(AR_KEYTABLE(_n) + 20)	/* key type */
#define	AR_KEYTABLE_TYPE_40	0x00000000	/* WEP 40 bit key */
#define	AR_KEYTABLE_TYPE_104	0x00000001	/* WEP 104 bit key */
#define	AR_KEYTABLE_TYPE_128	0x00000003	/* WEP 128 bit key */
#define	AR_KEYTABLE_TYPE_TKIP	0x00000004	/* TKIP and Michael */
#define	AR_KEYTABLE_TYPE_AES	0x00000005	/* AES/OCB 128 bit key */
#define	AR_KEYTABLE_TYPE_CCM	0x00000006	/* AES/CCM 128 bit key */
#define	AR_KEYTABLE_TYPE_CLR	0x00000007	/* no encryption */
#define	AR_KEYTABLE_ANT		0x00000008	/* previous transmit antenna */
#define	AR_KEYTABLE_MAC0(_n)	(AR_KEYTABLE(_n) + 24)	/* MAC address 1-32 */
#define	AR_KEYTABLE_MAC1(_n)	(AR_KEYTABLE(_n) + 28)	/* MAC address 33-47 */
#define	AR_KEYTABLE_VALID	0x00008000	/* key and MAC address valid */

/* Compress settings */
#define AR_CCFG_WIN_M           0x00000007 /* mask for AR_CCFG_WIN size */
#define AR_CCFG_MIB_INT_EN      0x00000008 /* compression performance MIB counter int enable */
#define AR_CCUCFG_RESET_VAL     0x00100200 /* the should be reset value */
#define AR_CCUCFG_CATCHUP_EN    0x00000001 /* Compression catchup enable */
#define AR_DCM_D_EN             0x00000001 /* all direct frames to be decompressed */
#define AR_COMPRESSION_WINDOW_SIZE      4096 /* default comp. window size */

#endif /* _DEV_AR5212REG_H_ */