ar5212.h.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

/*
 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
 * Copyright (c) 2002-2008 Atheros Communications, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 * $Id: ar5212.h,v 1.16 2008/11/22 07:42:00 sam Exp $
 */
#ifndef _ATH_AR5212_H_
#define _ATH_AR5212_H_

#include "ah_eeprom.h"

#define	AR5212_MAGIC	0x19541014

/* DCU Transmit Filter macros */
#define CALC_MMR(dcu, idx) \
	( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
#define TXBLK_FROM_MMR(mmr) \
	(AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
#define CALC_TXBLK_ADDR(dcu, idx)	(TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
#define CALC_TXBLK_VALUE(idx)		(1 << (idx & 0x1f))

/* MAC register values */

#define INIT_INTERRUPT_MASK \
	( AR_IMR_TXERR  | AR_IMR_TXOK | AR_IMR_RXORN | \
	  AR_IMR_RXERR  | AR_IMR_RXOK | AR_IMR_TXURN | \
	  AR_IMR_HIUERR )
#define INIT_BEACON_CONTROL \
	((INIT_RESET_TSF << 24)  | (INIT_BEACON_EN << 23) | \
	  (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)

#define INIT_CONFIG_STATUS	0x00000000
#define INIT_RSSI_THR		0x00000781	/* Missed beacon counter initialized to 0x7 (max is 0xff) */
#define INIT_IQCAL_LOG_COUNT_MAX	0xF
#define INIT_BCON_CNTRL_REG	0x00000000

#define INIT_USEC		40
#define HALF_RATE_USEC		19 /* ((40 / 2) - 1 ) */
#define QUARTER_RATE_USEC	9  /* ((40 / 4) - 1 ) */

#define RX_NON_FULL_RATE_LATENCY	63
#define TX_HALF_RATE_LATENCY		108
#define TX_QUARTER_RATE_LATENCY		216

#define IFS_SLOT_FULL_RATE	0x168 /* 9 us half, 40 MHz core clock (9*40) */
#define IFS_SLOT_HALF_RATE	0x104 /* 13 us half, 20 MHz core clock (13*20) */
#define IFS_SLOT_QUARTER_RATE	0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
#define IFS_EIFS_FULL_RATE	0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
#define IFS_EIFS_HALF_RATE	0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
#define IFS_EIFS_QUARTER_RATE	0xD48 /* (298 + (2 * 21)) * 10MHz core clock */

#define ACK_CTS_TIMEOUT_11A	0x3E8 /* ACK timeout in 11a core clocks */

/* Tx frame start to tx data start delay */
#define TX_FRAME_D_START_HALF_RATE 	0xc
#define TX_FRAME_D_START_QUARTER_RATE 	0xd

/*
 * Various fifo fill before Tx start, in 64-byte units
 * i.e. put the frame in the air while still DMAing
 */
#define MIN_TX_FIFO_THRESHOLD	0x1
#define MAX_TX_FIFO_THRESHOLD	((IEEE80211_MAX_LEN / 64) + 1)
#define INIT_TX_FIFO_THRESHOLD	MIN_TX_FIFO_THRESHOLD

#define	HAL_DECOMP_MASK_SIZE	128	/* 1 byte per key */

/*
 * Gain support.
 */
#define	NUM_CORNER_FIX_BITS		4
#define	NUM_CORNER_FIX_BITS_5112	7
#define	DYN_ADJ_UP_MARGIN		15
#define	DYN_ADJ_LO_MARGIN		20
#define	PHY_PROBE_CCK_CORRECTION	5
#define	CCK_OFDM_GAIN_DELTA		15

enum GAIN_PARAMS {
	GP_TXCLIP,
	GP_PD90,
	GP_PD84,
	GP_GSEL,
};

enum GAIN_PARAMS_5112 {
	GP_MIXGAIN_OVR,
	GP_PWD_138,
	GP_PWD_137,
	GP_PWD_136,
	GP_PWD_132,
	GP_PWD_131,
	GP_PWD_130,
};

typedef struct _gainOptStep {
	int16_t	paramVal[NUM_CORNER_FIX_BITS_5112];
	int32_t	stepGain;
	int8_t	stepName[16];
} GAIN_OPTIMIZATION_STEP;

typedef struct {
	uint32_t	numStepsInLadder;
	uint32_t	defaultStepNum;
	GAIN_OPTIMIZATION_STEP optStep[10];
} GAIN_OPTIMIZATION_LADDER;

typedef struct {
	uint32_t	currStepNum;
	uint32_t	currGain;
	uint32_t	targetGain;
	uint32_t	loTrig;
	uint32_t	hiTrig;
	uint32_t	gainFCorrection;
	uint32_t	active;
	const GAIN_OPTIMIZATION_STEP *currStep;
} GAIN_VALUES;

/* RF HAL structures */
typedef struct RfHalFuncs {
	void	  *priv;		/* private state */

	void	  (*rfDetach)(struct ath_hal *ah);
	void	  (*writeRegs)(struct ath_hal *,
			u_int modeIndex, u_int freqIndex, int regWrites);
	uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
	HAL_BOOL  (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
	HAL_BOOL  (*setRfRegs)(struct ath_hal *,
		      HAL_CHANNEL_INTERNAL *, uint16_t modesIndex,
		      uint16_t *rfXpdGain);
	HAL_BOOL  (*setPowerTable)(struct ath_hal *ah,
		      int16_t *minPower, int16_t *maxPower,
		      HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain);
	HAL_BOOL  (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *,
		      int16_t *maxPow, int16_t *minPow);
	int16_t	  (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
} RF_HAL_FUNCS;

struct ar5212AniParams {
	int		maxNoiseImmunityLevel;	/* [0..4] */
	int		totalSizeDesired[5];
	int		coarseHigh[5];
	int		coarseLow[5];
	int		firpwr[5];

	int		maxSpurImmunityLevel;	/* [0..7] */
	int		cycPwrThr1[8];

	int		maxFirstepLevel;	/* [0..2] */
	int		firstep[3];

	uint32_t	ofdmTrigHigh;
	uint32_t	ofdmTrigLow;
	uint32_t	cckTrigHigh;
	uint32_t	cckTrigLow;
	int32_t		rssiThrLow;
	uint32_t	rssiThrHigh;

	int		period;			/* update listen period */

	/* NB: intentionally ordered so data exported to user space is first */
	uint32_t	ofdmPhyErrBase;	/* Base value for ofdm err counter */
	uint32_t	cckPhyErrBase;	/* Base value for cck err counters */
};

/*
 * Per-channel ANI state private to the driver.
 */
struct ar5212AniState {
	uint8_t		noiseImmunityLevel;
	uint8_t		spurImmunityLevel;
	uint8_t		firstepLevel;
	uint8_t		ofdmWeakSigDetectOff;
	uint8_t		cckWeakSigThreshold;
	uint32_t	listenTime;

	/* NB: intentionally ordered so data exported to user space is first */
	HAL_CHANNEL	c;
	HAL_BOOL	isSetup;	/* has state to do a restore */
	uint32_t	txFrameCount;	/* Last txFrameCount */
	uint32_t	rxFrameCount;	/* Last rx Frame count */
	uint32_t	cycleCount;	/* Last cycleCount
					   (to detect wrap-around) */
	uint32_t	ofdmPhyErrCount;/* OFDM err count since last reset */
	uint32_t	cckPhyErrCount;	/* CCK err count since last reset */

	const struct ar5212AniParams *params;
};

#define	HAL_ANI_ENA		0x00000001	/* ANI operation enabled */
#define	HAL_RSSI_ANI_ENA	0x00000002	/* rssi-based processing ena'd*/

struct ar5212Stats {
	uint32_t	ast_ani_niup;	/* ANI increased noise immunity */
	uint32_t	ast_ani_nidown;	/* ANI decreased noise immunity */
	uint32_t	ast_ani_spurup;	/* ANI increased spur immunity */
	uint32_t	ast_ani_spurdown;/* ANI descreased spur immunity */
	uint32_t	ast_ani_ofdmon;	/* ANI OFDM weak signal detect on */
	uint32_t	ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
	uint32_t	ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
	uint32_t	ast_ani_ccklow;	/* ANI CCK weak signal threshold low */
	uint32_t	ast_ani_stepup;	/* ANI increased first step level */
	uint32_t	ast_ani_stepdown;/* ANI decreased first step level */
	uint32_t	ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
	uint32_t	ast_ani_cckerrs;/* ANI cumulative cck phy err count */
	uint32_t	ast_ani_reset;	/* ANI parameters zero'd for non-STA */
	uint32_t	ast_ani_lzero;	/* ANI listen time forced to zero */
	uint32_t	ast_ani_lneg;	/* ANI listen time calculated < 0 */
	HAL_MIB_STATS	ast_mibstats;	/* MIB counter stats */
	HAL_NODE_STATS	ast_nodestats;	/* Latest rssi stats from driver */
};

/*
 * NF Cal history buffer
 */
#define	AR5212_CCA_MAX_GOOD_VALUE	-95
#define	AR5212_CCA_MAX_HIGH_VALUE	-62
#define	AR5212_CCA_MIN_BAD_VALUE	-125

#define	AR512_NF_CAL_HIST_MAX		5

struct ar5212NfCalHist {
	int16_t		nfCalBuffer[AR512_NF_CAL_HIST_MAX];
	int16_t		privNF;
	uint8_t		currIndex;
	uint8_t		first_run;
	uint8_t		invalidNFcount;
};

struct ath_hal_5212 {
	struct ath_hal_private	ah_priv;	/* base class */

	/*
	 * Per-chip common Initialization data.
	 * NB: RF backends have their own ini data.
	 */
	HAL_INI_ARRAY	ah_ini_modes;
	HAL_INI_ARRAY	ah_ini_common;

	GAIN_VALUES	ah_gainValues;

	uint8_t		ah_macaddr[IEEE80211_ADDR_LEN];
	uint8_t		ah_bssid[IEEE80211_ADDR_LEN];
	uint8_t		ah_bssidmask[IEEE80211_ADDR_LEN];

	/*
	 * Runtime state.
	 */
	uint32_t	ah_maskReg;		/* copy of AR_IMR */
	struct ar5212Stats ah_stats;		/* various statistics */
	RF_HAL_FUNCS	*ah_rfHal;
	uint32_t	ah_txDescMask;		/* mask for TXDESC */
	uint32_t	ah_txOkInterruptMask;
	uint32_t	ah_txErrInterruptMask;
	uint32_t	ah_txDescInterruptMask;
	uint32_t	ah_txEolInterruptMask;
	uint32_t	ah_txUrnInterruptMask;
	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
	uint32_t	ah_intrTxqs;		/* tx q interrupt state */
						/* decomp mask array */
	uint8_t		ah_decompMask[HAL_DECOMP_MASK_SIZE];
	HAL_POWER_MODE	ah_powerMode;
	HAL_ANT_SETTING ah_antControl;		/* antenna setting */
	HAL_BOOL	ah_diversity;		/* fast diversity setting */
	enum {
		IQ_CAL_INACTIVE,
		IQ_CAL_RUNNING,
		IQ_CAL_DONE
	} ah_bIQCalibration;			/* IQ calibrate state */
	HAL_RFGAIN	ah_rfgainState;		/* RF gain calibrartion state */
	uint32_t	ah_tx6PowerInHalfDbm;	/* power output for 6Mb tx */
	uint32_t	ah_staId1Defaults;	/* STA_ID1 default settings */
	uint32_t	ah_miscMode;		/* MISC_MODE settings */
	uint32_t	ah_rssiThr;		/* RSSI_THR settings */
	HAL_BOOL	ah_cwCalRequire;	/* for ap51 */
	HAL_BOOL	ah_tpcEnabled;		/* per-packet tpc enabled */
	HAL_BOOL	ah_phyPowerOn;		/* PHY power state */
	HAL_BOOL	ah_isHb63;		/* cached HB63 check */
	uint32_t	ah_macTPC;		/* tpc register */
	uint32_t	ah_beaconInterval;	/* XXX */
	enum {
		AUTO_32KHZ,		/* use it if 32kHz crystal present */
		USE_32KHZ,		/* do it regardless */
		DONT_USE_32KHZ,		/* don't use it regardless */
	} ah_enable32kHzClock;			/* whether to sleep at 32kHz */
	uint32_t	ah_ofdmTxPower;
	int16_t		ah_txPowerIndexOffset;
	/*
	 * Noise floor cal histogram support.
	 */
	struct ar5212NfCalHist ah_nfCalHist;