ah_eeprom_v3.c.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

			pNumTrgtChannels = &ee->ee_numTargetPwr_11a;
			break;
		case headerInfo11B:
			if (!enable24)
				continue;
			off += GROUP6_OFFSET;
			nchan = 2;
			pPowerInfo = ee->ee_trgtPwr_11b;
			pNumTrgtChannels = &ee->ee_numTargetPwr_11b;
			break;
		case headerInfo11G:
			if (!enable24)
				continue;
			off += GROUP7_OFFSET;
			nchan = 3;
			pPowerInfo = ee->ee_trgtPwr_11g;
			pNumTrgtChannels = &ee->ee_numTargetPwr_11g;
			break;
		default:
			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
			    __func__, mode);
			return AH_FALSE;
		}
		*pNumTrgtChannels = 0;
		for (i = 0; i < nchan; i++) {
			EEREAD(off++);
			if (ee->ee_version >= AR_EEPROM_VER3_3) {
				pPowerInfo->testChannel = (eeval >> 8) & 0xff;
			} else {
				pPowerInfo->testChannel = (eeval >> 9) & 0x7f;
			}

			if (pPowerInfo->testChannel != 0) {
				/* get the channel value and read rest of info */
				if (mode == headerInfo11A) {
					pPowerInfo->testChannel = fbin2freq(ee, pPowerInfo->testChannel);
				} else {
					pPowerInfo->testChannel = fbin2freq_2p4(ee, pPowerInfo->testChannel);
				}

				if (ee->ee_version >= AR_EEPROM_VER3_3) {
					pPowerInfo->twicePwr6_24 = (eeval >> 2) & POWER_MASK;
					pPowerInfo->twicePwr36   = (eeval << 4) & POWER_MASK;
				} else {
					pPowerInfo->twicePwr6_24 = (eeval >> 3) & POWER_MASK;
					pPowerInfo->twicePwr36   = (eeval << 3) & POWER_MASK;
				}

				EEREAD(off++);
				if (ee->ee_version >= AR_EEPROM_VER3_3) {
					pPowerInfo->twicePwr36 |= (eeval >> 12) & 0xf;
					pPowerInfo->twicePwr48 = (eeval >> 6) & POWER_MASK;
					pPowerInfo->twicePwr54 =  eeval & POWER_MASK;
				} else {
					pPowerInfo->twicePwr36 |= (eeval >> 13) & 0x7;
					pPowerInfo->twicePwr48 = (eeval >> 7) & POWER_MASK;
					pPowerInfo->twicePwr54 = (eeval >> 1) & POWER_MASK;
				}
				(*pNumTrgtChannels)++;
			}
			pPowerInfo++;
		}
	}
	return AH_TRUE;
#undef EEREAD
}

/*
 * Now copy EEPROM Coformance Testing Limits contents 
 * into the allocated space
 */
static HAL_BOOL
readEepromCTLInfo(struct ath_hal *ah, HAL_EEPROM *ee)
{
#define	EEREAD(_off) do {				\
	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
		return AH_FALSE;			\
} while (0)
	RD_EDGES_POWER *rep;
	uint16_t eeval;
	uint32_t off;
	int i, j;

	rep = ee->ee_rdEdgesPower;

	off = GROUP8_OFFSET +
		(ee->ee_version >= AR_EEPROM_VER4_0 ?
			ee->ee_targetPowersStart - GROUP5_OFFSET :
	         ee->ee_version >= AR_EEPROM_VER3_3 ?
			GROUPS_OFFSET3_3 : GROUPS_OFFSET3_2);
	for (i = 0; i < ee->ee_numCtls; i++) {
		if (ee->ee_ctl[i] == 0) {
			/* Move offset and edges */
			off += (ee->ee_version >= AR_EEPROM_VER3_3 ? 8 : 7);
			rep += NUM_EDGES;
			continue;
		}
		if (ee->ee_version >= AR_EEPROM_VER3_3) {
			for (j = 0; j < NUM_EDGES; j += 2) {
				EEREAD(off++);
				rep[j].rdEdge = (eeval >> 8) & FREQ_MASK_3_3;
				rep[j+1].rdEdge = eeval & FREQ_MASK_3_3;
			}
			for (j = 0; j < NUM_EDGES; j += 2) {
				EEREAD(off++);
				rep[j].twice_rdEdgePower = 
					(eeval >> 8) & POWER_MASK;
				rep[j].flag = (eeval >> 14) & 1;
				rep[j+1].twice_rdEdgePower = eeval & POWER_MASK;
				rep[j+1].flag = (eeval >> 6) & 1;
			}
		} else { 
			EEREAD(off++);
			rep[0].rdEdge = (eeval >> 9) & FREQ_MASK;
			rep[1].rdEdge = (eeval >> 2) & FREQ_MASK;
			rep[2].rdEdge = (eeval << 5) & FREQ_MASK;

			EEREAD(off++);
			rep[2].rdEdge |= (eeval >> 11) & 0x1f;
			rep[3].rdEdge = (eeval >> 4) & FREQ_MASK;
			rep[4].rdEdge = (eeval << 3) & FREQ_MASK;

			EEREAD(off++);
			rep[4].rdEdge |= (eeval >> 13) & 0x7;
			rep[5].rdEdge = (eeval >> 6) & FREQ_MASK;
			rep[6].rdEdge = (eeval << 1) & FREQ_MASK;

			EEREAD(off++);
			rep[6].rdEdge |= (eeval >> 15) & 0x1;
			rep[7].rdEdge = (eeval >> 8) & FREQ_MASK;

			rep[0].twice_rdEdgePower = (eeval >> 2) & POWER_MASK;
			rep[1].twice_rdEdgePower = (eeval << 4) & POWER_MASK;

			EEREAD(off++);
			rep[1].twice_rdEdgePower |= (eeval >> 12) & 0xf;
			rep[2].twice_rdEdgePower = (eeval >> 6) & POWER_MASK;
			rep[3].twice_rdEdgePower = eeval & POWER_MASK;

			EEREAD(off++);
			rep[4].twice_rdEdgePower = (eeval >> 10) & POWER_MASK;
			rep[5].twice_rdEdgePower = (eeval >> 4) & POWER_MASK;
			rep[6].twice_rdEdgePower = (eeval << 2) & POWER_MASK;

			EEREAD(off++);
			rep[6].twice_rdEdgePower |= (eeval >> 14) & 0x3;
			rep[7].twice_rdEdgePower = (eeval >> 8) & POWER_MASK;
		}

		for (j = 0; j < NUM_EDGES; j++ ) {
			if (rep[j].rdEdge != 0 || rep[j].twice_rdEdgePower != 0) {
				if ((ee->ee_ctl[i] & CTL_MODE_M) == CTL_11A ||
				    (ee->ee_ctl[i] & CTL_MODE_M) == CTL_TURBO) {
					rep[j].rdEdge = fbin2freq(ee, rep[j].rdEdge);
				} else {
					rep[j].rdEdge = fbin2freq_2p4(ee, rep[j].rdEdge);
				}
			}
		}
		rep += NUM_EDGES;
	}
	return AH_TRUE;
#undef EEREAD
}

/*
 * Read the individual header fields for a Rev 3 EEPROM
 */
static HAL_BOOL
readHeaderInfo(struct ath_hal *ah, HAL_EEPROM *ee)
{
#define	EEREAD(_off) do {				\
	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
		return AH_FALSE;			\
} while (0)
	static const uint32_t headerOffset3_0[] = {
		0x00C2, /* 0 - Mode bits, device type, max turbo power */
		0x00C4, /* 1 - 2.4 and 5 antenna gain */
		0x00C5, /* 2 - Begin 11A modal section */
		0x00D0, /* 3 - Begin 11B modal section */
		0x00DA, /* 4 - Begin 11G modal section */
		0x00E4  /* 5 - Begin CTL section */
	};
	static const uint32_t headerOffset3_3[] = {
		0x00C2, /* 0 - Mode bits, device type, max turbo power */
		0x00C3, /* 1 - 2.4 and 5 antenna gain */
		0x00D4, /* 2 - Begin 11A modal section */
		0x00F2, /* 3 - Begin 11B modal section */
		0x010D, /* 4 - Begin 11G modal section */
		0x0128  /* 5 - Begin CTL section */
	};

	static const uint32_t regCapOffsetPre4_0 = 0x00CF;
	static const uint32_t regCapOffsetPost4_0 = 0x00CA; 

	const uint32_t *header;
	uint32_t off;
	uint16_t eeval;
	int i;

	/* initialize cckOfdmGainDelta for < 4.2 eeprom */
	ee->ee_cckOfdmGainDelta = CCK_OFDM_GAIN_DELTA;
	ee->ee_scaledCh14FilterCckDelta = TENX_CH14_FILTER_CCK_DELTA_INIT;

	if (ee->ee_version >= AR_EEPROM_VER3_3) {
		header = headerOffset3_3;
		ee->ee_numCtls = NUM_CTLS_3_3;
	} else {
		header = headerOffset3_0;
		ee->ee_numCtls = NUM_CTLS;
	}
	HALASSERT(ee->ee_numCtls <= NUM_CTLS_MAX);

	EEREAD(header[0]);
	ee->ee_turbo5Disable	= (eeval >> 15) & 0x01;
	ee->ee_rfKill		= (eeval >> 14) & 0x01;
	ee->ee_deviceType	= (eeval >> 11) & 0x07;
	ee->ee_turbo2WMaxPower5	= (eeval >> 4) & 0x7F;
	if (ee->ee_version >= AR_EEPROM_VER4_0)
		ee->ee_turbo2Disable	= (eeval >> 3) & 0x01;
	else
		ee->ee_turbo2Disable	= 1;
	ee->ee_Gmode		= (eeval >> 2) & 0x01;
	ee->ee_Bmode		= (eeval >> 1) & 0x01;
	ee->ee_Amode		= (eeval & 0x01);

	off = header[1];
	EEREAD(off++);
	ee->ee_antennaGainMax[0] = (int8_t)((eeval >> 8) & 0xFF);
	ee->ee_antennaGainMax[1] = (int8_t)(eeval & 0xFF);
	if (ee->ee_version >= AR_EEPROM_VER4_0) {
		EEREAD(off++);
		ee->ee_eepMap		 = (eeval>>14) & 0x3;
		ee->ee_disableXr5	 = (eeval>>13) & 0x1;
		ee->ee_disableXr2	 = (eeval>>12) & 0x1;
		ee->ee_earStart		 = eeval & 0xfff;

		EEREAD(off++);
		ee->ee_targetPowersStart = eeval & 0xfff;
		ee->ee_exist32kHzCrystal = (eeval>>14) & 0x1;

		if (ee->ee_version >= AR_EEPROM_VER5_0) {
			off += 2;
			EEREAD(off);
			ee->ee_eepMap2PowerCalStart = (eeval >> 4) & 0xfff;
			/* Properly cal'ed 5.0 devices should be non-zero */
		}
	}

	/* Read the moded sections of the EEPROM header in the order A, B, G */
	for (i = headerInfo11A; i <= headerInfo11G; i++) {
		/* Set the offset via the index */
		off = header[2 + i];

		EEREAD(off++);
		ee->ee_switchSettling[i] = (eeval >> 8) & 0x7f;
		ee->ee_txrxAtten[i] = (eeval >> 2) & 0x3f;
		ee->ee_antennaControl[0][i] = (eeval << 4) & 0x3f;

		EEREAD(off++);
		ee->ee_antennaControl[0][i] |= (eeval >> 12) & 0x0f;
		ee->ee_antennaControl[1][i] = (eeval >> 6) & 0x3f;
		ee->ee_antennaControl[2][i] = eeval & 0x3f;

		EEREAD(off++);
		ee->ee_antennaControl[3][i] = (eeval >> 10)  & 0x3f;
		ee->ee_antennaControl[4][i] = (eeval >> 4)  & 0x3f;
		ee->ee_antennaControl[5][i] = (eeval << 2)  & 0x3f;

		EEREAD(off++);
		ee->ee_antennaControl[5][i] |= (eeval >> 14)  & 0x03;
		ee->ee_antennaControl[6][i] = (eeval >> 8)  & 0x3f;
		ee->ee_antennaControl[7][i] = (eeval >> 2)  & 0x3f;
		ee->ee_antennaControl[8][i] = (eeval << 4)  & 0x3f;

		EEREAD(off++);
		ee->ee_antennaControl[8][i] |= (eeval >> 12)  & 0x0f;
		ee->ee_antennaControl[9][i] = (eeval >> 6)  & 0x3f;
		ee->ee_antennaControl[10][i] = eeval & 0x3f;

		EEREAD(off++);
		ee->ee_adcDesiredSize[i] = (int8_t)((eeval >> 8)  & 0xff);
		switch (i) {
		case headerInfo11A:
			ee->ee_ob4 = (eeval >> 5)  & 0x07;
			ee->ee_db4 = (eeval >> 2)  & 0x07;
			ee->ee_ob3 = (eeval << 1)  & 0x07;
			break;
		case headerInfo11B:
			ee->ee_obFor24 = (eeval >> 4)  & 0x07;
			ee->ee_dbFor24 = eeval & 0x07;
			break;
		case headerInfo11G:
			ee->ee_obFor24g = (eeval >> 4)  & 0x07;
			ee->ee_dbFor24g = eeval & 0x07;
			break;
		}

		if (i == headerInfo11A) {
			EEREAD(off++);
			ee->ee_ob3 |= (eeval >> 15)  & 0x01;
			ee->ee_db3 = (eeval >> 12)  & 0x07;
			ee->ee_ob2 = (eeval >> 9)  & 0x07;
			ee->ee_db2 = (eeval >> 6)  & 0x07;
			ee->ee_ob1 = (eeval >> 3)  & 0x07;
			ee->ee_db1 = eeval & 0x07;
		}

		EEREAD(off++);
		ee->ee_txEndToXLNAOn[i] = (eeval >> 8)  & 0xff;
		ee->ee_thresh62[i] = eeval & 0xff;

		EEREAD(off++);
		ee->ee_txEndToXPAOff[i] = (eeval >> 8)  & 0xff;
		ee->ee_txFrameToXPAOn[i] = eeval  & 0xff;

		EEREAD(off++);
		ee->ee_pgaDesiredSize[i] = (int8_t)((eeval >> 8)  & 0xff);
		ee->ee_noiseFloorThresh[i] = eeval  & 0xff;
		if (ee->ee_noiseFloorThresh[i] & 0x80) {
			ee->ee_noiseFloorThresh[i] = 0 -
				((ee->ee_noiseFloorThresh[i] ^ 0xff) + 1);
		}

		EEREAD(off++);
		ee->ee_xlnaGain[i] = (eeval >> 5)  & 0xff;
		ee->ee_xgain[i] = (eeval >> 1)  & 0x0f;
		ee->ee_xpd[i] = eeval  & 0x01;
		if (ee->ee_version >= AR_EEPROM_VER4_0) {
			switch (i) {
			case headerInfo11A:
				ee->ee_fixedBias5 = (eeval >> 13) & 0x1;
				break;
			case headerInfo11G:
				ee->ee_fixedBias2 = (eeval >> 13) & 0x1;
				break;
			}
		}

		if (ee->ee_version >= AR_EEPROM_VER3_3) {
			EEREAD(off++);
			ee->ee_falseDetectBackoff[i] = (eeval >> 6) & 0x7F;
			switch (i) {
			case headerInfo11B:
				ee->ee_ob2GHz[0] = eeval & 0x7;
				ee->ee_db2GHz[0] = (eeval >> 3) & 0x7;
				break;
			case headerInfo11G:
				ee->ee_ob2GHz[1] = eeval & 0x7;
				ee->ee_db2GHz[1] = (eeval >> 3) & 0x7;
				break;
			case headerInfo11A:
				ee->ee_xrTargetPower5 = eeval & 0x3f;
				break;
			}
		}
		if (ee->ee_version >= AR_EEPROM_VER3_4) {
			ee->ee_gainI[i] = (eeval >> 13) & 0x07;

			EEREAD(off++);
			ee->ee_gainI[i] |= (eeval << 3) & 0x38;
			if (i == headerInfo11G) {
				ee->ee_cckOfdmPwrDelta = (eeval >> 3) & 0xFF;
				if (ee->ee_version >= AR_EEPROM_VER4_6)
					ee->ee_scaledCh14FilterCckDelta =
						(eeval >> 11) & 0x1f;
			}
			if (i == headerInfo11A &&
			    ee->ee_version >= AR_EEPROM_VER4_0) {
				ee->ee_iqCalI[0] = (eeval >> 8 ) & 0x3f;
				ee->ee_iqCalQ[0] = (eeval >> 3 ) & 0x1f;
			}
		} else {
			ee->ee_gainI[i] = 10;
			ee->ee_cckOfdmPwrDelta = TENX_OFDM_CCK_DELTA_INIT;
		}
		if (ee->ee_version >= AR_EEPROM_VER4_0) {
			switch (i) {
			case headerInfo11B:
				EEREAD(off++);
				ee->ee_calPier11b[0] =
					fbin2freq_2p4(ee, eeval&0xff);
				ee->ee_calPier11b[1] =
					fbin2freq_2p4(ee, (eeval >> 8)&0xff);
				EEREAD(off++);
				ee->ee_calPier11b[2] =
					fbin2freq_2p4(ee, eeval&0xff);
				if (ee->ee_version >= AR_EEPROM_VER4_1)
					ee->ee_rxtxMargin[headerInfo11B] =
						(eeval >> 8) & 0x3f;
				break;
			case headerInfo11G:
				EEREAD(off++);
				ee->ee_calPier11g[0] =
					fbin2freq_2p4(ee, eeval & 0xff);
				ee->ee_calPier11g[1] =
					fbin2freq_2p4(ee, (eeval >> 8) & 0xff);

				EEREAD(off++);
				ee->ee_turbo2WMaxPower2 = eeval & 0x7F;
				ee->ee_xrTargetPower2 = (eeval >> 7) & 0x3f;

				EEREAD(off++);
				ee->ee_calPier11g[2] =
					fbin2freq_2p4(ee, eeval & 0xff);
				if (ee->ee_version >= AR_EEPROM_VER4_1)
					 ee->ee_rxtxMargin[headerInfo11G] =
						(eeval >> 8) & 0x3f;

				EEREAD(off++);
				ee->ee_iqCalI[1] = (eeval >> 5) & 0x3F;
				ee->ee_iqCalQ[1] = eeval & 0x1F;

				if (ee->ee_version >= AR_EEPROM_VER4_2) {
					EEREAD(off++);
					ee->ee_cckOfdmGainDelta =
						(uint8_t)(eeval & 0xFF);
					if (ee->ee_version >= AR_EEPROM_VER5_0) {
						ee->ee_switchSettlingTurbo[1] =
							(eeval >> 8) & 0x7f;
						ee->ee_txrxAttenTurbo[1] =
							(eeval >> 15) & 0x1;
						EEREAD(off++);
						ee->ee_txrxAttenTurbo[1] |=
							(eeval & 0x1F) << 1;
						ee->ee_rxtxMarginTurbo[1] =
							(eeval >> 5) & 0x3F;
						ee->ee_adcDesiredSizeTurbo[1] =
							(eeval >> 11) & 0x1F;
						EEREAD(off++);
						ee->ee_adcDesiredSizeTurbo[1] |=
							(eeval & 0x7) << 5;
						ee->ee_pgaDesiredSizeTurbo[1] =
							(eeval >> 3) & 0xFF;
					}
				}
				break;
			case headerInfo11A:
				if (ee->ee_version >= AR_EEPROM_VER4_1) {
					EEREAD(off++);
					ee->ee_rxtxMargin[headerInfo11A] =
						eeval & 0x3f;
					if (ee->ee_version >= AR_EEPROM_VER5_0) {
						ee->ee_switchSettlingTurbo[0] =
							(eeval >> 6) & 0x7f;
						ee->ee_txrxAttenTurbo[0] =
							(eeval >> 13) & 0x7;
						EEREAD(off++);
						ee->ee_txrxAttenTurbo[0] |=
							(eeval & 0x7) << 3;
						ee->ee_rxtxMarginTurbo[0] =
							(eeval >> 3) & 0x3F;
						ee->ee_adcDesiredSizeTurbo[0] =
							(eeval >> 9) & 0x7F;
						EEREAD(off++);
						ee->ee_adcDesiredSizeTurbo[0] |=
							(eeval & 0x1) << 7;
						ee->ee_pgaDesiredSizeTurbo[0] =
							(eeval >> 1) & 0xFF;
					}
				}
				break;
			}
		}
	}
	if (ee->ee_version < AR_EEPROM_VER3_3) {
		/* Version 3.1+ specific parameters */
		EEREAD(0xec);
		ee->ee_ob2GHz[0] = eeval & 0x7;
		ee->ee_db2GHz[0] = (eeval >> 3) & 0x7;