📄 ah_regdomain.c.svn-base

📁 最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码
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#define	F2_5260_5700	AFTER(F1_5260_5700)	{ 5260, 5700, 5,  6,  5,  5, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },#define	F3_5260_5700	AFTER(F2_5260_5700)	{ 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },#define	F1_5280_5320	AFTER(F3_5260_5700)	{ 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },#define	F1_5500_5620	AFTER(F1_5280_5320)	{ 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4 },#define	F1_5500_5700	AFTER(F1_5500_5620)	{ 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },#define	F2_5500_5700	AFTER(F1_5500_5700)	{ 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },#define	F3_5500_5700	AFTER(F2_5500_5700)	{ 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0 },#define	F4_5500_5700	AFTER(F3_5500_5700)	{ 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F1_5745_5805	AFTER(F4_5500_5700)	{ 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F2_5745_5805	AFTER(F1_5745_5805)	{ 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },#define	F3_5745_5805	AFTER(F2_5745_5805)	{ 5745, 5825, 5,  6, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F1_5745_5825	AFTER(F3_5745_5805)	{ 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F2_5745_5825	AFTER(F1_5745_5825)	{ 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F3_5745_5825	AFTER(F2_5745_5825)	{ 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F4_5745_5825	AFTER(F3_5745_5825)	{ 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3 },#define	F5_5745_5825	AFTER(F4_5745_5825)	{ 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },#define	F6_5745_5825	AFTER(F5_5745_5825)	{ 5745, 5825, 5,  6, 10, 10, NO_DFS, NO_PSCAN, 0 },#define	F7_5745_5825	AFTER(F6_5745_5825)	{ 5745, 5825, 5,  6,  5,  5, NO_DFS, NO_PSCAN, 0 },#define	F8_5745_5825	AFTER(F7_5745_5825)	{ 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN, 3 },#define	F9_5745_5825	AFTER(F8_5745_5825)	{ 5745, 5825, 30, 6, 20,  5, NO_DFS, NO_PSCAN, 3 },#define	F10_5745_5825	AFTER(F9_5745_5825)	/*	 * Below are the world roaming channels	 * All WWR domains have no power limit, instead use the card's CTL	 * or max power settings.	 */	{ 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },#define	W1_4920_4980	AFTER(F10_5745_5825)	{ 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },#define	W1_5040_5080	AFTER(W1_4920_4980)	{ 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },#define	W1_5170_5230	AFTER(W1_5040_5080)	{ 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },#define	W1_5180_5240	AFTER(W1_5170_5230)	{ 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },#define	W1_5260_5320	AFTER(W1_5180_5240)	{ 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },#define	W1_5745_5825	AFTER(W1_5260_5320)	{ 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },#define	W1_5500_5700	AFTER(W1_5745_5825)	{ 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN,  0 },#define	W2_5260_5320	AFTER(W1_5500_5700)	{ 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN,  0 },#define	W2_5180_5240	AFTER(W2_5260_5320)	{ 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },#define	W2_5825_5825	AFTER(W2_5180_5240)};/* * 5GHz Turbo (dynamic & static) tags */static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {	{ 5130, 5210, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5130_5210	0	{ 5250, 5330, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},#define	T1_5250_5330	AFTER(T1_5130_5210)	{ 5370, 5490, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5370_5490	AFTER(T1_5250_5330)	{ 5530, 5650, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},#define	T1_5530_5650	AFTER(T1_5370_5490)	{ 5150, 5190, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5150_5190	AFTER(T1_5530_5650)	{ 5230, 5310, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},#define	T1_5230_5310	AFTER(T1_5150_5190)	{ 5350, 5470, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5350_5470	AFTER(T1_5230_5310)	{ 5510, 5670, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},#define	T1_5510_5670	AFTER(T1_5350_5470)	{ 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5200_5240	AFTER(T1_5510_5670)	{ 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T2_5200_5240	AFTER(T1_5200_5240)	{ 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5210_5210	AFTER(T2_5200_5240)	{ 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T2_5210_5210	AFTER(T1_5210_5210)	{ 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T1_5280_5280	AFTER(T2_5210_5210)	{ 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T2_5280_5280	AFTER(T1_5280_5280)	{ 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T1_5250_5250	AFTER(T2_5280_5280)	{ 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T1_5290_5290	AFTER(T1_5250_5250)	{ 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T1_5250_5290	AFTER(T1_5290_5290)	{ 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T2_5250_5290	AFTER(T1_5250_5290)	{ 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},#define	T1_5540_5660	AFTER(T2_5250_5290)	{ 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5760_5800	AFTER(T1_5540_5660)	{ 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T2_5760_5800	AFTER(T1_5760_5800)	{ 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},#define	T1_5765_5805	AFTER(T2_5760_5800)	/*	 * Below are the WWR frequencies	 */	{ 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},#define	WT1_5210_5250	AFTER(T1_5765_5805)	{ 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},#define	WT1_5290_5290	AFTER(WT1_5210_5250)	{ 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},#define	WT1_5540_5660	AFTER(WT1_5290_5290)	{ 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0},#define	WT1_5760_5800	AFTER(WT1_5540_5660)};/* * 2GHz 11b channel tags */static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {	{ 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2312_2372	0	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F2_2312_2372	AFTER(F1_2312_2372)	{ 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2412_2472	AFTER(F2_2312_2372)	{ 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},#define	F2_2412_2472	AFTER(F1_2412_2472)	{ 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F3_2412_2472	AFTER(F2_2412_2472)	{ 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2412_2462	AFTER(F3_2412_2472)	{ 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},#define	F2_2412_2462	AFTER(F1_2412_2462)	{ 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2432_2442	AFTER(F2_2412_2462)	{ 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2457_2472	AFTER(F1_2432_2442)	{ 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0},#define	F1_2467_2472	AFTER(F1_2457_2472)	{ 2484, 2484, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2484_2484	AFTER(F1_2467_2472)	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0},#define	F2_2484_2484	AFTER(F1_2484_2484)	{ 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	F1_2512_2732	AFTER(F2_2484_2484)	/*	 * WWR have powers opened up to 20dBm.	 * Limits should often come from CTL/Max powers	 */	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	W1_2312_2372	AFTER(F1_2512_2732)	{ 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	W1_2412_2412	AFTER(W1_2312_2372)	{ 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	W1_2417_2432	AFTER(W1_2412_2412)	{ 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	W1_2437_2442	AFTER(W1_2417_2432)	{ 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	W1_2447_2457	AFTER(W1_2437_2442)	{ 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	W1_2462_2462	AFTER(W1_2447_2457)	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},#define	W1_2467_2467	AFTER(W1_2462_2462)	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},#define	W2_2467_2467	AFTER(W1_2467_2467)	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},#define	W1_2472_2472	AFTER(W2_2467_2467)	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},#define	W2_2472_2472	AFTER(W1_2472_2472)	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},#define	W1_2484_2484	AFTER(W2_2472_2472)	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},#define	W2_2484_2484	AFTER(W1_2484_2484)};/* * 2GHz 11g channel tags */static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {	{ 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G1_2312_2372	0	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G2_2312_2372	AFTER(G1_2312_2372)	{ 2312, 2372, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},#define	G3_2312_2372	AFTER(G2_2312_2372)	{ 2312, 2372, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},#define	G4_2312_2372	AFTER(G3_2312_2372)	{ 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G1_2412_2472	AFTER(G4_2312_2372)	{ 2412, 2472, 20, 0, 20, 5,  NO_DFS, PSCAN_MKKA_G, 0},#define	G2_2412_2472	AFTER(G1_2412_2472)	{ 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G3_2412_2472	AFTER(G2_2412_2472)	{ 2412, 2472, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},#define	G4_2412_2472	AFTER(G3_2412_2472)	{ 2412, 2472, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},#define	G5_2412_2472	AFTER(G4_2412_2472)	{ 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G1_2412_2462	AFTER(G5_2412_2472)	{ 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},#define	G2_2412_2462	AFTER(G1_2412_2462)	{ 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN, 0},#define	G3_2412_2462	AFTER(G2_2412_2462)	{ 2412, 2462, 27, 6,  5, 5, NO_DFS, NO_PSCAN, 0},#define	G4_2412_2462	AFTER(G3_2412_2462)		{ 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G1_2432_2442	AFTER(G4_2412_2462)	{ 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G1_2457_2472	AFTER(G1_2432_2442)	{ 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},#define	G1_2512_2732	AFTER(G1_2457_2472)	{ 2512, 2732, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},#define	G2_2512_2732	AFTER(G1_2512_2732)	{ 2512, 2732, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},#define	G3_2512_2732	AFTER(G2_2512_2732)	{ 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0 },#define	G1_2467_2472	AFTER(G3_2512_2732)	/*	 * WWR open up the power to 20dBm	 */	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	WG1_2312_2372	AFTER(G1_2467_2472)	{ 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	WG1_2412_2412	AFTER(WG1_2312_2372)	{ 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	WG1_2417_2432	AFTER(WG1_2412_2412)	{ 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	WG1_2437_2442	AFTER(WG1_2417_2432)	{ 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	WG1_2447_2457	AFTER(WG1_2437_2442)	{ 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},#define	WG1_2462_2462	AFTER(WG1_2447_2457)	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},#define	WG1_2467_2467	AFTER(WG1_2462_2462)	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},#define	WG2_2467_2467	AFTER(WG1_2467_2467)	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},#define	WG1_2472_2472	AFTER(WG2_2467_2467)	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},#define	WG2_2472_2472	AFTER(WG1_2472_2472)	/*	 * Mapping for 900MHz cards like Ubiquiti SR9 and XR9	 * and ZComax GZ-901.	 */	{ 2422, 2437, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },#define	S1_907_922_5	AFTER(WG2_2472_2472)	{ 2422, 2437, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },#define	S1_907_922_10	AFTER(S1_907_922_5)	{ 2427, 2432, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },#define	S1_912_917	AFTER(S1_907_922_10)	{ 2427, 2442, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },#define	S2_907_922_5	AFTER(S1_912_917)	{ 2427, 2442, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },#define	S2_907_922_10	AFTER(S2_907_922_5)	{ 2432, 2437, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
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