if_ath_hal_extensions.h.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

static inline void set_field(struct ath_hal *ah, u_int32_t reg, u_int32_t mask, u_int32_t shift, u_int32_t value) {
	OS_REG_WRITE(ah, reg, 
			  (OS_REG_READ(ah, reg) & ~mask) | 
			  ((value << shift) & mask));
}

static inline u_int32_t field_eq(struct ath_hal *ah, u_int32_t reg, 
				 u_int32_t mask, u_int32_t shift, 
				 u_int32_t value, int is_signed) {
	return  (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)) == 
		(value & (mask >> shift));
}

static inline void override_warning(struct ath_hal *ah, const char *name,
				    u_int32_t reg, u_int32_t mask,
				    u_int32_t shift, u_int32_t expected, int is_signed) {

	if (!field_eq(ah, reg, mask, shift, expected, is_signed)) 
		printk("%s: Correcting 0x%04x[%s] from 0x%x (%d) to 0x%x (%d).\n", 
		       SC_DEV_NAME(ah->ah_sc),
		       reg,
		       name, 
		       (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
		       get_field(ah, reg, mask, shift, is_signed), 
		       (expected & (mask >> shift)), /* not sign extended */
		       expected);
#if 0 /* NB: For checking to see if HAL is fixed or not */
	else {
			printk("%s: Keeping 0x%04x[%s] - 0x%x (%d).\n",
			       SC_DEV_NAME(ah->ah_sc),
			       reg,
			       name, 
			       (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)),
			       get_field(ah, reg, mask, shift, is_signed));
	}
#endif
}

static inline void verification_warning(struct ath_hal *ah, const char *name,
    u_int32_t reg, u_int32_t mask, 
    u_int32_t shift, u_int32_t expected, int is_signed) {

	int ret = field_eq(ah, reg, mask, shift, expected, is_signed);
	if (!ret) {
		printk("%s: %s verification of %s default value "
		       "[found=0x%x (%d) expected=0x%x (%d)].\n", 
		       SC_DEV_NAME(ah->ah_sc),
		       (ret ? "PASSED" : "FAILED"),
			name, 
		       (get_field(ah, reg, mask, shift, is_signed) & (mask >> shift)), 
		       get_field(ah, reg, mask, shift, is_signed), 
		       (expected & (mask >> shift)), /* not sign extended */
		       expected);
		ath_hal_print_decoded_register(ah, NULL, reg, 
					       OS_REG_READ(ah, reg), OS_REG_READ(ah, reg), 0);
	}
}

#define GET_FIELD(ah, __reg, __mask, __signed) \
	get_field(ah, __reg, __mask, __mask ## _S, __signed)
#define SET_FIELD(ah, __reg, __mask, __value) \
	set_field(ah, __reg, __mask, __mask ## _S, __value);
#define FIELD_EQ(ah, __reg, __mask, __value, __signed) \
	field_eq(ah, __reg, __mask, __mask ## _S, __value, __signed)

#if 0 /* NB: These are working at this point, and HAL tweaks them a lot */
#define OVERRIDE_WARNING(ah, __reg, __mask, __expected, __signed) \
	override_warning(ah, #__mask, __reg, __mask, __mask ## _S, __expected, __signed)
#else
#define OVERRIDE_WARNING(ah, __reg, __mask, __expected, __signed) 
#endif
	
#define VERIFICATION_WARNING(ah, __reg, __mask, __signed) \
	verification_warning(ah, #__mask, __reg, __mask, __mask ## _S, DEFAULT_ ## __mask, __signed)
#define VERIFICATION_WARNING_SW(ah, __reg, __mask, __signed) \
	verification_warning(ah, #__mask, __reg, __mask, __mask ## _S, DEFAULT_ENABLE_ ## __reg ? __mask ## _ON : __mask ## _OFF, __signed)

static inline void ath_hal_set_noise_immunity(struct ath_hal *ah,
					      int agc_desired_size, 
					      int agc_coarse_hi,
					      int agc_coarse_lo, 
					      int sig_firpwr) 
{
	ATH_HAL_LOCK_IRQ(ah->ah_sc);
	ath_hal_set_function(__func__);
	ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));

#if 0 /* NB: These are working at this point, and HAL tweaks them a lot */
	OVERRIDE_WARNING(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, agc_desired_size, 1);
	OVERRIDE_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, agc_coarse_lo, 1);
	OVERRIDE_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, agc_coarse_hi, 1);
	OVERRIDE_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, sig_firpwr, 1);
#endif

	SET_FIELD(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, agc_desired_size);
	SET_FIELD(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, agc_coarse_lo);
	SET_FIELD(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, agc_coarse_hi);
	SET_FIELD(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, sig_firpwr);

	ath_hal_set_function(NULL);
	ath_hal_set_device(NULL);
	ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
}

static inline void ath_hal_set_ofdm_weak_det(struct ath_hal *ah, 
	int low_m1, int low_m2, int low_m2_count, int low_self_corr,
	int high_m1, int high_m2, int high_m2_count)
{
	ATH_HAL_LOCK_IRQ(ah->ah_sc);
	ath_hal_set_function(__func__);
	ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));

	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, low_m1, 0);
	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, low_m2, 0);
	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, low_m2_count, 0);
	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, low_self_corr, 0);
	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, high_m1, 0);
	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, high_m2, 0);
	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, high_m2_count, 0);

	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, low_m1);
	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, low_m2);
	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, low_m2_count);
	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, low_self_corr);
	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, high_m1);
	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, high_m2);
	SET_FIELD(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, high_m2_count);

	ath_hal_set_function(NULL);
	ath_hal_set_device(NULL);
	ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
}

static inline void ath_hal_set_cck_weak_det(struct ath_hal *ah, int thresh)
{
	ATH_HAL_LOCK_IRQ(ah->ah_sc);
	ath_hal_set_function(__func__);
	ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));

	OVERRIDE_WARNING(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, thresh, 0);

	SET_FIELD(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, thresh);

	ath_hal_set_function(NULL);
	ath_hal_set_device(NULL);
	ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
}

static inline void ath_hal_set_sig_firstep(struct ath_hal *ah, int firstep)
{
	ATH_HAL_LOCK_IRQ(ah->ah_sc);
	ath_hal_set_function(__func__);
	ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));

	OVERRIDE_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, firstep, 0);

	SET_FIELD(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, firstep);

	ath_hal_set_function(NULL);
	ath_hal_set_device(NULL);
	ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
}

static inline void ath_hal_set_spur_immunity(struct ath_hal *ah, int thresh)
{
	ATH_HAL_LOCK_IRQ(ah->ah_sc);
	ath_hal_set_function(__func__);
	ath_hal_set_device(SC_DEV_NAME(ah->ah_sc));

	OVERRIDE_WARNING(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, thresh, 0);

	SET_FIELD(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, thresh);

	ath_hal_set_function(NULL);
	ath_hal_set_device(NULL);
	ATH_HAL_UNLOCK_IRQ(ah->ah_sc);
}

static inline void ath_hal_restore_default_noise_immunity(struct ath_hal *ah) {

	ath_hal_set_noise_immunity(ah, 
		DEFAULT_AR5K_PHY_AGCSIZE_DESIRED, 
		DEFAULT_AR5K_PHY_AGCCOARSE_HI,
		DEFAULT_AR5K_PHY_AGCCOARSE_LO,
		DEFAULT_AR5K_PHY_SIG_FIRPWR);
}

static inline void ath_hal_enable_ofdm_weak_det(struct ath_hal *ah, int enable) {
	if (enable)
		ath_hal_set_ofdm_weak_det(ah, 
			AR5K_PHY_WEAK_OFDM_LOW_M1_ON,
			AR5K_PHY_WEAK_OFDM_LOW_M2_ON,
			AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_ON,
		        AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_ON,
			AR5K_PHY_WEAK_OFDM_HIGH_M1_ON,
			AR5K_PHY_WEAK_OFDM_HIGH_M2_ON,
			AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_ON);
	else
		ath_hal_set_ofdm_weak_det(ah, 
			AR5K_PHY_WEAK_OFDM_LOW_M1_OFF,
			AR5K_PHY_WEAK_OFDM_LOW_M2_OFF,
			AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT_OFF,
			AR5K_PHY_WEAK_OFDM_LOW_SELFCOR_OFF,
			AR5K_PHY_WEAK_OFDM_HIGH_M1_OFF,
			AR5K_PHY_WEAK_OFDM_HIGH_M2_OFF,
			AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT_OFF);
}

static inline void ath_hal_enable_cck_weak_det(struct ath_hal *ah, int enable) {
	ath_hal_set_cck_weak_det(ah, enable 
				 ? AR5K_PHY_WEAK_CCK_THRESH_ON 
				 : AR5K_PHY_WEAK_CCK_THRESH_OFF);
}

static inline void ath_hal_restore_default_ofdm_weak_det(struct ath_hal *ah) {
	ath_hal_enable_ofdm_weak_det(ah, DEFAULT_ENABLE_AR5K_PHY_WEAK_OFDM);
}

static inline void ath_hal_restore_default_cck_weak_det(struct ath_hal *ah) {
	ath_hal_enable_cck_weak_det(ah, DEFAULT_ENABLE_AR5K_PHY_WEAK_CCK);
}

static inline void ath_hal_restore_default_sig_firstep(struct ath_hal *ah) {

	ath_hal_set_sig_firstep(ah, 
		DEFAULT_AR5K_PHY_SIG_FIRSTEP);
}

static inline void ath_hal_restore_default_spur_immunity(struct ath_hal *ah) {

	ath_hal_set_spur_immunity(ah, 
		DEFAULT_AR5K_PHY_SPUR_THRESH);
}

static inline void ath_hal_restore_default_intmit(struct ath_hal *ah) {
	ath_hal_restore_default_noise_immunity(ah);
	ath_hal_restore_default_ofdm_weak_det(ah);
	ath_hal_restore_default_cck_weak_det(ah);
	ath_hal_restore_default_sig_firstep(ah);
	ath_hal_restore_default_spur_immunity(ah);

}

static inline void ath_hal_verify_default_intmit(struct ath_hal *ah) {
	/* Just a list of all the fields above, for sanity checks... */
	VERIFICATION_WARNING(ah, AR5K_PHY_AGCSIZE, AR5K_PHY_AGCSIZE_DESIRED, 1);
	VERIFICATION_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_LO, 1);
	VERIFICATION_WARNING(ah, AR5K_PHY_AGCCOARSE, AR5K_PHY_AGCCOARSE_HI, 1);
	VERIFICATION_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRPWR, 1);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M1, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_M2_COUNT, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_LOW, AR5K_PHY_WEAK_OFDM_LOW_SELFCOR, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M1, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_OFDM_HIGH, AR5K_PHY_WEAK_OFDM_HIGH_M2_COUNT, 0);
	VERIFICATION_WARNING_SW(ah, AR5K_PHY_WEAK_CCK, AR5K_PHY_WEAK_CCK_THRESH, 0);
	VERIFICATION_WARNING(ah, AR5K_PHY_SIG, AR5K_PHY_SIG_FIRSTEP, 0);
	VERIFICATION_WARNING(ah, AR5K_PHY_SPUR, AR5K_PHY_SPUR_THRESH, 0);
}

static inline void ath_hal_set_dmasize_pcie(struct ath_hal *ah) {
	SET_FIELD(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
	SET_FIELD(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
}

#endif /* _IF_ATH_HAL_EXTENSIONS_H_ */