ath_info.c.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

		break;
	case AR5K_EEPROM_MODE_11G:
		offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
						AR5K_EEPROM_GROUP4_OFFSET;
		gen_chan_info = ee->ee_pwr_cal_g;
		/* Fixed cal piers */
		gen_chan_info[0].freq = 2312;
		gen_chan_info[1].freq = 2412;
		gen_chan_info[2].freq = 2484;
		ee->ee_cal_piers_b = 3;
		cal_piers = ee->ee_cal_piers_g;
		break;
	default:
		return -EINVAL;
	}

	for (i = 0; i < cal_piers; i++) {

		gen_chan_info[i].rf5111_info =
				malloc(sizeof(struct ath5k_chan_pcal_info_rf5111));

		chan_pcal_info = gen_chan_info[i].rf5111_info;

		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pcdac_max     = (u_int16_t)((val >> 10) & 0x3f);
		chan_pcal_info->pcdac_min    = (u_int16_t)((val >> 4) & 0x3f);
		chan_pcal_info->pwr[0] = (u_int16_t)((val << 2) & 0x3f);

		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pwr[0] |= (u_int16_t)((val >> 14) & 0x3);
		chan_pcal_info->pwr[1] = (u_int16_t)((val >> 8) & 0x3f);
		chan_pcal_info->pwr[2] = (u_int16_t)((val >> 2) & 0x3f);
		chan_pcal_info->pwr[3] = (u_int16_t)((val << 4) & 0x3f);

		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pwr[3] |= (u_int16_t)((val >> 12) & 0xf);
		chan_pcal_info->pwr[4] = (u_int16_t)((val >> 6) & 0x3f);
		chan_pcal_info->pwr[5] = (u_int16_t)(val  & 0x3f);

		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pwr[6] = (u_int16_t)((val >> 10) & 0x3f);
		chan_pcal_info->pwr[7] = (u_int16_t)((val >> 4) & 0x3f);
		chan_pcal_info->pwr[8] = (u_int16_t)((val << 2) & 0x3f);

		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pwr[8] |= (u_int16_t)((val >> 14) & 0x3);
		chan_pcal_info->pwr[9] = (u_int16_t)((val >> 8) & 0x3f);
		chan_pcal_info->pwr[10] = (u_int16_t)((val >> 2) & 0x3f);

		/* Recreate pcdac offsets table for this channel
		 * using intercepts table and PCDAC min/max */
		for (c = 0; c < AR5K_EEPROM_N_PWR_POINTS_5111; c++ )
			chan_pcal_info->pcdac[c] =
				(intercepts[c] * chan_pcal_info->pcdac_max + 
				(100 - intercepts[c]) * chan_pcal_info->pcdac_min) / 100;
	}

	return 0;

}

static int ath5k_eeprom_read_rf5112_pcal_info(struct ath5k_eeprom_info *ee,
							unsigned int mode)
{
	u_int32_t offset;
	unsigned int i, c;
	int ret;
	u_int16_t val;
	struct	ath5k_chan_pcal_info *gen_chan_info;
	struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
	u_int16_t cal_piers;

	switch (mode) {
	case AR5K_EEPROM_MODE_11A:
		/*
		 * Read 5GHz EEPROM channels
		 */
		offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
		ee->ee_cal_piers_a = 0;
		for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
			AR5K_EEPROM_READ(offset++, val);

			if ((val & 0xff) == 0)
				break;

			ee->ee_pwr_cal_a[i].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff,
						AR5K_EEPROM_MODE_11A);
			ee->ee_cal_piers_a++;

			if (((val >> 8) & 0xff) == 0)
				break;

			ee->ee_pwr_cal_a[++i].freq =
				ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
							AR5K_EEPROM_MODE_11A);
			ee->ee_cal_piers_a++;

		}
		offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
						AR5K_EEPROM_GROUP2_OFFSET;
		gen_chan_info = ee->ee_pwr_cal_a;
		cal_piers = ee->ee_cal_piers_a;
		break;
	case AR5K_EEPROM_MODE_11B:

		if (AR5K_EEPROM_HDR_11A(ee->ee_header))		
			offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
							AR5K_EEPROM_GROUP3_OFFSET;
		else
			offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);

		gen_chan_info = ee->ee_pwr_cal_b;
		cal_piers = ee->ee_cal_piers_b;
		break;
	case AR5K_EEPROM_MODE_11G:

		if (AR5K_EEPROM_HDR_11A(ee->ee_header))	{	
			offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
						AR5K_EEPROM_GROUP4_OFFSET;
		} else if (AR5K_EEPROM_HDR_11B(ee->ee_header)) {
			offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
						AR5K_EEPROM_GROUP2_OFFSET;
		} else
			offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
			
		gen_chan_info = ee->ee_pwr_cal_g;
		cal_piers = ee->ee_cal_piers_g;
		break;
	default:
		return -EINVAL;
	}

	for (i = 0; i < cal_piers; i++) {

		gen_chan_info[i].rf5112_info =
				malloc(sizeof(struct ath5k_chan_pcal_info_rf5112));

		chan_pcal_info = gen_chan_info[i].rf5112_info;

		/* Power values in dBm * 4 
		 * for the lower xpd gain curve
		 * (0 dBm -> higher output power) */
		for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pwr_x0[c] = (val & 0xff);
			chan_pcal_info->pwr_x0[++c] = ((val >> 8) & 0xff);
		}

		/* PCDAC steps
		 * corresponding to the above power
		 * measurements */
		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
		chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
		chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);

		/* Power values in dBm * 4
		 * for the higher xpd gain curve
		 * (18 dBm -> lower output power) */
		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pwr_x3[0] = (val & 0xff);
		chan_pcal_info->pwr_x3[1] = ((val >> 8) & 0xff);

		AR5K_EEPROM_READ(offset++, val);
		chan_pcal_info->pwr_x3[2] = (val & 0xff);

		/* PCDAC steps
		 * corresponding to the above power
		 * measurements (static) */
		chan_pcal_info->pcdac_x3[0] = 20;
		chan_pcal_info->pcdac_x3[1] = 35;
		chan_pcal_info->pcdac_x3[2] = 63;

		if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
			chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0xff);

			/* Last xpd0 power level is also channel maximum */
			gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
		} else {
			chan_pcal_info->pcdac_x0[0] = 1;
			gen_chan_info[i].max_pwr = ((val >> 8) & 0xff);
		}

		/* Recreate pcdac_x0 table for this channel using pcdac steps */
		chan_pcal_info->pcdac_x0[1] += chan_pcal_info->pcdac_x0[0];
		chan_pcal_info->pcdac_x0[2] += chan_pcal_info->pcdac_x0[1];
		chan_pcal_info->pcdac_x0[3] += chan_pcal_info->pcdac_x0[2];
	}

	return 0;
}

static int ath5k_eeprom_read_rf2413_pcal_info(struct ath5k_eeprom_info *ee,
							unsigned int mode)
{
	u_int32_t offset, start_offset;
	unsigned int i, c;
	int ret;
	u_int16_t val;
	struct	ath5k_chan_pcal_info *gen_chan_info;
	struct ath5k_chan_pcal_info_rf2413 *chan_pcal_info;
	u_int16_t cal_piers;
	u_int8_t pd_gains = 0;

	if (ee->ee_x_gain[mode] & 0x1) pd_gains++;
	if ((ee->ee_x_gain[mode] >> 1) & 0x1) pd_gains++;
	if ((ee->ee_x_gain[mode] >> 2) & 0x1) pd_gains++;
	if ((ee->ee_x_gain[mode] >> 3) & 0x1) pd_gains++;

	switch (mode) {
	case AR5K_EEPROM_MODE_11A:
		start_offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
		offset = start_offset;
		ee->ee_cal_piers_a = 0;

		if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
			return 0;

		for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
			AR5K_EEPROM_READ(offset++, val);

			if ((val & 0xff) == 0)
				break;

			ee->ee_pwr_cal_a[i].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff,
						AR5K_EEPROM_MODE_11A);
			ee->ee_cal_piers_a++;

			if (((val >> 8) & 0xff) == 0)
				break;

			ee->ee_pwr_cal_a[++i].freq =
				ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
							AR5K_EEPROM_MODE_11A);
			ee->ee_cal_piers_a++;

		}
		offset = start_offset + (AR5K_EEPROM_N_5GHZ_CHAN / 2);
		gen_chan_info = ee->ee_pwr_cal_a;
		cal_piers = ee->ee_cal_piers_a;
		break;
	case AR5K_EEPROM_MODE_11B:
		start_offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);

		if (AR5K_EEPROM_HDR_11A(ee->ee_header))
			start_offset +=	(ee->ee_cal_piers_a * (3 * ee->ee_pwr_cal_a[0].rf2413_info->pd_gains) +
						(ee->ee_pwr_cal_a[0].rf2413_info->pd_gains == 1 ? 1 : 0)) + 5;

		offset = start_offset;
		ee->ee_cal_piers_b = 0;

		if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
			return 0;

		for (i = 0; i < AR5K_EEPROM_N_2GHZ_CHAN_2413; i++) {
			AR5K_EEPROM_READ(offset++, val);

			if ((val & 0xff) == 0)
				break;

			ee->ee_pwr_cal_b[i].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff,
						AR5K_EEPROM_MODE_11B);
			ee->ee_cal_piers_b++;

			if (((val >> 8) & 0xff) == 0)
				break;

			ee->ee_pwr_cal_b[++i].freq =
				ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
							AR5K_EEPROM_MODE_11B);
			ee->ee_cal_piers_b++;

		}
		offset = start_offset + (AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2);
		gen_chan_info = ee->ee_pwr_cal_b;
		cal_piers = ee->ee_cal_piers_b;
		break;
	case AR5K_EEPROM_MODE_11G:
		start_offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);

		if (AR5K_EEPROM_HDR_11A(ee->ee_header))
			start_offset +=	(ee->ee_cal_piers_a * (3 * ee->ee_pwr_cal_a[0].rf2413_info->pd_gains) +
							(ee->ee_pwr_cal_a[0].rf2413_info->pd_gains == 1 ? 1 : 0)) + 5;

		if (AR5K_EEPROM_HDR_11B(ee->ee_header))
			start_offset +=	(ee->ee_cal_piers_b * (3 * ee->ee_pwr_cal_b[0].rf2413_info->pd_gains) +
							(ee->ee_pwr_cal_b[0].rf2413_info->pd_gains == 1 ? 1 : 0)) + 2;

		offset = start_offset;
		ee->ee_cal_piers_g = 0;

		if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
			return 0;

		for (i = 0; i < AR5K_EEPROM_N_2GHZ_CHAN_2413; i++) {
			AR5K_EEPROM_READ(offset++, val);

			if ((val & 0xff) == 0)
				break;

			ee->ee_pwr_cal_g[i].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff,
						AR5K_EEPROM_MODE_11G);
			ee->ee_cal_piers_g++;

			if (((val >> 8) & 0xff) == 0)
				break;

			ee->ee_pwr_cal_g[++i].freq =
				ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
							AR5K_EEPROM_MODE_11G);
			ee->ee_cal_piers_g++;

		}
		offset = start_offset + (AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2);
		gen_chan_info = ee->ee_pwr_cal_g;
		cal_piers = ee->ee_cal_piers_g;
		break;
	default:
		return -EINVAL;
	}

	for (i = 0; i < cal_piers; i++) {

		gen_chan_info[i].rf2413_info =
				malloc(sizeof(struct ath5k_chan_pcal_info_rf2413));

		chan_pcal_info = gen_chan_info[i].rf2413_info;

		chan_pcal_info->pd_gains = pd_gains;

		if (chan_pcal_info->pd_gains > 0) {
			/*
			 * Read pwr_i, pddac_i and the first
			 * 2 pd points (pwr, pddac)
			 */
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pwr_i[0] = val & 0x1f;
			chan_pcal_info->pddac_i[0] = (val >> 5) & 0x7f;
			chan_pcal_info->pwr[0][0] =
						(val >> 12) & 0xf;

			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pddac[0][0] = val & 0x3f;
			chan_pcal_info->pwr[0][1] = (val >> 6) & 0xf;
			chan_pcal_info->pddac[0][1] =
						(val >> 10) & 0x3f;
			
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pwr[0][2] = val & 0xf;
			chan_pcal_info->pddac[0][2] =
						(val >> 4) & 0x3f;

			chan_pcal_info->pwr[0][3] = 0;
			chan_pcal_info->pddac[0][3] = 0;
		}
		
		if (chan_pcal_info->pd_gains > 1) {
			/*
			 * Pd gain 0 is not the last pd gain
			 * so it only has 2 pd points.
			 * Continue wih pd gain 1.
			 */
			chan_pcal_info->pwr_i[1] = (val >> 10) & 0x1f;

			chan_pcal_info->pddac_i[1] = (val >> 15) & 0x1;
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pddac_i[1] |= (val & 0x3F) << 1;

			chan_pcal_info->pwr[1][0] = (val >> 6) & 0xf;
			chan_pcal_info->pddac[1][0] =
						(val >> 10) & 0x3f;
			
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pwr[1][1] = val & 0xf;
			chan_pcal_info->pddac[1][1] =
						(val >> 4) & 0x3f;
			chan_pcal_info->pwr[1][2] =
						(val >> 10) & 0xf;

			chan_pcal_info->pddac[1][2] =
						(val >> 14) & 0x3;
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pddac[1][2] |=
						(val & 0xF) << 2;

			chan_pcal_info->pwr[1][3] = 0;
			chan_pcal_info->pddac[1][3] = 0;
		} else if (chan_pcal_info->pd_gains == 1) {
			/*
			 * Pd gain 0 is the last one so
			 * read the extra point.
			 */
			chan_pcal_info->pwr[0][3] =
						(val >> 10) & 0xf;

			chan_pcal_info->pddac[0][3] =
						(val >> 14) & 0x3;
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pddac[0][3] |=
						(val & 0xF) << 2;
		}

		/*
		 * Proceed with the other pd_gains
		 * as above.
		 */
		if (chan_pcal_info->pd_gains > 2) {
			chan_pcal_info->pwr_i[2] = (val >> 4) & 0x1f;
			chan_pcal_info->pddac_i[2] = (val >> 9) & 0x7f;
			
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pwr[2][0] =
						(val >> 0) & 0xf;
			chan_pcal_info->pddac[2][0] =
						(val >> 4) & 0x3f;
			chan_pcal_info->pwr[2][1] =
						(val >> 10) & 0xf;

			chan_pcal_info->pddac[2][1] =
						(val >> 14) & 0x3;
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pddac[2][1] |=
						(val & 0xF) << 2;

			chan_pcal_info->pwr[2][2] =
						(val >> 4) & 0xf;
			chan_pcal_info->pddac[2][2] =
						(val >> 8) & 0x3f;

			chan_pcal_info->pwr[2][3] = 0;
			chan_pcal_info->pddac[2][3] = 0;
		} else if (chan_pcal_info->pd_gains == 2) {
			chan_pcal_info->pwr[1][3] =
						(val >> 4) & 0xf;
			chan_pcal_info->pddac[1][3] =
						(val >> 8) & 0x3f;
		}

		if (chan_pcal_info->pd_gains > 3) {
			chan_pcal_info->pwr_i[3] = (val >> 14) & 0x3;
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pwr_i[3] |= ((val >> 0) & 0x7) << 2;

			chan_pcal_info->pddac_i[3] = (val >> 3) & 0x7f;
			chan_pcal_info->pwr[3][0] =
						(val >> 10) & 0xf;
			chan_pcal_info->pddac[3][0] =
						(val >> 14) & 0x3;
			
			AR5K_EEPROM_READ(offset++, val);
			chan_pcal_info->pddac[3][0] |=
						(val & 0xF) << 2;
			chan_pcal_info->pwr[3][1] =
						(val >> 4) & 0xf;
			chan_pcal_info->pddac[3][1] =