ath_info.c.svn-base

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

}

/*
 * Translate binary channel representation in EEPROM to frequency
 */
static u_int16_t ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee,
				       u_int16_t bin, unsigned int mode)
{
	u_int16_t val;

	if (bin == AR5K_EEPROM_CHANNEL_DIS)
		return bin;

	if (mode == AR5K_EEPROM_MODE_11A) {
		if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
			val = (5 * bin) + 4800;
		else
			val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
			    (bin * 10) + 5100;
	} else {
		if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
			val = bin + 2300;
		else
			val = bin + 2400;
	}

	return val;
}

/*
 * Read antenna info from EEPROM
 */
static int ath5k_eeprom_read_ants(struct ath5k_eeprom_info *ee,
				  u_int32_t *offset, unsigned int mode)
{
	u_int32_t o = *offset;
	u_int16_t val;
	int ret, i = 0;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_switch_settling[mode]	= (val >> 8) & 0x7f;
	ee->ee_atn_tx_rx[mode]		= (val >> 2) & 0x3f;
	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
	ee->ee_ant_control[mode][i++]	= val & 0x3f;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_ant_control[mode][i++]	= (val >> 10) & 0x3f;
	ee->ee_ant_control[mode][i++]	= (val >> 4) & 0x3f;
	ee->ee_ant_control[mode][i]	= (val << 2) & 0x3f;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_ant_control[mode][i++]	|= (val >> 14) & 0x3;
	ee->ee_ant_control[mode][i++]	= (val >> 8) & 0x3f;
	ee->ee_ant_control[mode][i++]	= (val >> 2) & 0x3f;
	ee->ee_ant_control[mode][i]	= (val << 4) & 0x3f;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_ant_control[mode][i++]	|= (val >> 12) & 0xf;
	ee->ee_ant_control[mode][i++]	= (val >> 6) & 0x3f;
	ee->ee_ant_control[mode][i++]	= val & 0x3f;

	/* Get antenna modes */
	ee->ee_antenna[mode][0] =
	    (ee->ee_ant_control[mode][0] << 4) | 0x1;
	ee->ee_antenna[mode][AR5K_ANT_FIXED_A] =
	     ee->ee_ant_control[mode][1]	|
	    (ee->ee_ant_control[mode][2] << 6)	|
	    (ee->ee_ant_control[mode][3] << 12) |
	    (ee->ee_ant_control[mode][4] << 18) |
	    (ee->ee_ant_control[mode][5] << 24);
	ee->ee_antenna[mode][AR5K_ANT_FIXED_B] =
	     ee->ee_ant_control[mode][6]	|
	    (ee->ee_ant_control[mode][7] << 6)	|
	    (ee->ee_ant_control[mode][8] << 12) |
	    (ee->ee_ant_control[mode][9] << 18) |
	    (ee->ee_ant_control[mode][10] << 24);

	/* return new offset */
	*offset = o;

	return 0;
}

/*
 * Read supported modes from EEPROM
 */
static int ath5k_eeprom_read_modes(struct ath5k_eeprom_info *ee,
				   u_int32_t *offset, unsigned int mode)
{
	u_int32_t o = *offset;
	u_int16_t val;
	int ret;

	switch (mode){
	case AR5K_EEPROM_MODE_11A:
		AR5K_EEPROM_READ(o++, val);
		ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
		ee->ee_ob[mode][3]		= (val >> 5) & 0x7;
		ee->ee_db[mode][3]		= (val >> 2) & 0x7;
		ee->ee_ob[mode][2]		= (val << 1) & 0x7;

		AR5K_EEPROM_READ(o++, val);
		ee->ee_ob[mode][2]		|= (val >> 15) & 0x1;
		ee->ee_db[mode][2]		= (val >> 12) & 0x7;
		ee->ee_ob[mode][1]		= (val >> 9) & 0x7;
		ee->ee_db[mode][1]		= (val >> 6) & 0x7;
		ee->ee_ob[mode][0]		= (val >> 3) & 0x7;
		ee->ee_db[mode][0]		= val & 0x7;
		break;
	case AR5K_EEPROM_MODE_11B:
		AR5K_EEPROM_READ(o++, val);
		ee->ee_adc_desired_size[mode]	= (int8_t)((val >> 8) & 0xff);
		ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
		ee->ee_db[mode][1]		= val & 0x7;
		break;
	case AR5K_EEPROM_MODE_11G:
		AR5K_EEPROM_READ(o++, val);
		ee->ee_adc_desired_size[mode]	= (signed short int)((val >> 8) & 0xff);
		ee->ee_ob[mode][1]		= (val >> 4) & 0x7;
		ee->ee_db[mode][1]		= val & 0x7;
		break;
	}

	AR5K_EEPROM_READ(o++, val);
	ee->ee_tx_end2xlna_enable[mode]	= (val >> 8) & 0xff;
	ee->ee_thr_62[mode]		= val & 0xff;

	if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2)
		ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_tx_end2xpa_disable[mode]	= (val >> 8) & 0xff;
	ee->ee_tx_frm2xpa_enable[mode]	= val & 0xff;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_pga_desired_size[mode]	= (val >> 8) & 0xff;

	if ((val & 0xff) & 0x80)
		ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
	else
		ee->ee_noise_floor_thr[mode] = val & 0xff;

	if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2)
		ee->ee_noise_floor_thr[mode] =
		    mode == AR5K_EEPROM_MODE_11A ? -54 : -1;

	AR5K_EEPROM_READ(o++, val);
	ee->ee_xlna_gain[mode]		= (val >> 5) & 0xff;
	ee->ee_x_gain[mode]		= (val >> 1) & 0xf;
	ee->ee_xpd[mode]		= val & 0x1;

	if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
		ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;

	if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
		AR5K_EEPROM_READ(o++, val);
		ee->ee_false_detect[mode] = (val >> 6) & 0x7f;

		if (mode == AR5K_EEPROM_MODE_11A)
			ee->ee_xr_power[mode] = val & 0x3f;
		else {
			ee->ee_ob[mode][0] = val & 0x7;
			ee->ee_db[mode][0] = (val >> 3) & 0x7;
		}
	}

	if (ee->ee_version < AR5K_EEPROM_VERSION_3_4) {
		ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
		ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
	} else {
		ee->ee_i_gain[mode] = (val >> 13) & 0x7;

		AR5K_EEPROM_READ(o++, val);
		ee->ee_i_gain[mode] |= (val << 3) & 0x38;

		if (mode == AR5K_EEPROM_MODE_11G) {
			ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;

			if (ee->ee_version >= AR5K_EEPROM_VERSION_4_6)
				ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
		}
	}

	if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0 &&
	    mode == AR5K_EEPROM_MODE_11A) {
		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
	}

	if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0) {
		switch (mode) {
		case AR5K_EEPROM_MODE_11B:
			AR5K_EEPROM_READ(o++, val);

			ee->ee_cal_piers_b = 0;

			ee->ee_pwr_cal_b[0].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
			if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
				ee->ee_cal_piers_b++;

			ee->ee_pwr_cal_b[1].freq =
				ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
			if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
				ee->ee_cal_piers_b++;

			AR5K_EEPROM_READ(o++, val);
			ee->ee_pwr_cal_b[2].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
			if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
				ee->ee_cal_piers_b++;
			break;
		case AR5K_EEPROM_MODE_11G:
			AR5K_EEPROM_READ(o++, val);

			ee->ee_cal_piers_g = 0;

			ee->ee_pwr_cal_g[0].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
			if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
				ee->ee_cal_piers_g++;

			ee->ee_pwr_cal_g[1].freq =
				ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
			if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
				ee->ee_cal_piers_g++;

			AR5K_EEPROM_READ(o++, val);
			ee->ee_turbo_max_power[mode] = val & 0x7f;
			ee->ee_xr_power[mode] = (val >> 7) & 0x3f;

			AR5K_EEPROM_READ(o++, val);
			ee->ee_pwr_cal_g[2].freq =
				ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
			if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
				ee->ee_cal_piers_g++;
			break;
		}
	}

	if (ee->ee_version >= AR5K_EEPROM_VERSION_4_1) {
		switch (mode) {
		case AR5K_EEPROM_MODE_11A:
			AR5K_EEPROM_READ(o++, val);
			ee->ee_margin_tx_rx[mode] = val & 0x3f;
			break;
		case AR5K_EEPROM_MODE_11B:
		case AR5K_EEPROM_MODE_11G:
			ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
			break;
		}
	}

	if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0 &&
	    mode == AR5K_EEPROM_MODE_11G) {
		AR5K_EEPROM_READ(o++, val);
		ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
		ee->ee_q_cal[mode] = (val >> 3) & 0x1f;

		if (ee->ee_version >= AR5K_EEPROM_VERSION_4_2) {
			AR5K_EEPROM_READ(o++, val);
			ee->ee_cck_ofdm_gain_delta = val & 0xff;
		}
	}

	/* return new offset */
	*offset = o;

	return 0;
}

/*
 * Read turbo mode information on newer EEPROM versions
 */
static int ath5k_eeprom_read_turbo_modes(struct ath5k_eeprom_info *ee,
				   u_int32_t *offset, unsigned int mode)
{
	u_int32_t o = *offset;
	u_int16_t val;
	int ret;

	if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
		return 0;

	switch (mode){
	case AR5K_EEPROM_MODE_11A:
		ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;

		ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
		AR5K_EEPROM_READ(o++, val);
		ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
		ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;

		ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
		AR5K_EEPROM_READ(o++, val);
		ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
		ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;

		if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
			ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
		break;
	case AR5K_EEPROM_MODE_11G:
		ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;

		ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
		AR5K_EEPROM_READ(o++, val);
		ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
		ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;

		ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
		AR5K_EEPROM_READ(o++, val);
		ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
		ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
		break;
	}

	/* return new offset */
	*offset = o;

	return 0;
}

/*
 * Read per channel calibration info from EEPROM
 *
 * This info is used to calibrate the baseband power table. Imagine
 * that for each channel there is a power curve that's hw specific
 * (depends on amplifier) and we try to "correct" this curve using offests
 * we pass on to phy chip (baseband -> before amplifier) so that it can
 * use accurate power values when setting tx power (takes amplifier's
 * performance on each channel into account).
 *
 * EEPROM provides us with the offsets for some pre-calibrated channels
 * and we have to scale (to create the full table for these channels) and
 * interpolate (in order to create the table for any channel).
 */

static int ath5k_eeprom_read_rf5111_pcal_info(struct ath5k_eeprom_info *ee,
							unsigned int mode)
{
	u_int32_t offset;
	unsigned int i, c;
	int ret;
	u_int16_t val;
	struct	ath5k_chan_pcal_info *gen_chan_info;
	struct ath5k_chan_pcal_info_rf5111 *chan_pcal_info;
	u_int16_t cal_piers;
	/* Fixed percentage intercepts */
	static const u_int8_t intercepts_3[] =
		{ 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
	static const u_int8_t intercepts_3_2[] =
		{ 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
	const u_int8_t *intercepts =
		ee->ee_version < AR5K_EEPROM_VERSION_3_2 ?
			intercepts_3 : intercepts_3_2;

	switch (mode) {
	case AR5K_EEPROM_MODE_11A:
		/*
		 * Read 5GHz EEPROM channels
		 */
		offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
		gen_chan_info = ee->ee_pwr_cal_a;
		ee->ee_cal_piers_a = 0;
		/* Different frequency mask for < 3.2 */
		if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
			AR5K_EEPROM_READ(offset++, val);
			gen_chan_info[0].freq =
				ath5k_eeprom_bin2freq(ee, val >> 9 & 0x7f,
						AR5K_EEPROM_MODE_11A);
			gen_chan_info[1].freq =
				ath5k_eeprom_bin2freq(ee, val >> 2 & 0x7f,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[2].freq = val << 5 & 0x7f;
			AR5K_EEPROM_READ(offset++, val);
			gen_chan_info[2].freq |= val >> 11 & 0x1f;
			gen_chan_info[2].freq =
			ath5k_eeprom_bin2freq(ee, gen_chan_info[2].freq,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[3].freq =
				ath5k_eeprom_bin2freq(ee, val >> 4 & 0x7f,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[4].freq = val << 3 & 0x7f;
			AR5K_EEPROM_READ(offset++, val);
			gen_chan_info[4].freq |= val >> 13 & 0x7;
			gen_chan_info[4].freq =
				ath5k_eeprom_bin2freq(ee, gen_chan_info[4].freq,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[5].freq =
				ath5k_eeprom_bin2freq(ee, val >> 6 & 0x7f,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[6].freq = val << 1 & 0x7f;
			AR5K_EEPROM_READ(offset++, val);
			gen_chan_info[6].freq |= val >> 15 & 0x1;
			gen_chan_info[6].freq =
				ath5k_eeprom_bin2freq(ee, gen_chan_info[6].freq,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[7].freq =
				ath5k_eeprom_bin2freq(ee, val >> 8 & 0x7f,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[8].freq =
				ath5k_eeprom_bin2freq(ee, val >> 1 & 0x7f,
						AR5K_EEPROM_MODE_11A);

			gen_chan_info[9].freq = val << 6 & 0x7f;
			AR5K_EEPROM_READ(offset++, val);
			gen_chan_info[9].freq |= val >> 10 & 0x3f;
			gen_chan_info[9].freq =
				ath5k_eeprom_bin2freq(ee, gen_chan_info[9].freq,
						AR5K_EEPROM_MODE_11A);

			ee->ee_cal_piers_a = 10;
		} else {
			for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
				AR5K_EEPROM_READ(offset++, val);

				if ((val & 0xff) == 0)
					break;

				ee->ee_pwr_cal_a[i].freq =
					ath5k_eeprom_bin2freq(ee, val & 0xff,
							AR5K_EEPROM_MODE_11A);
				ee->ee_cal_piers_a++;

				if (((val >> 8) & 0xff) == 0)
					break;

				ee->ee_pwr_cal_a[++i].freq =
					ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff,
								AR5K_EEPROM_MODE_11A);
				ee->ee_cal_piers_a++;

			}
		}
		offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
						AR5K_EEPROM_GROUP2_OFFSET;
		cal_piers = ee->ee_cal_piers_a;
		break;
	case AR5K_EEPROM_MODE_11B:
		offset = AR5K_EEPROM_GROUPS_START(ee->ee_version) +
						AR5K_EEPROM_GROUP3_OFFSET;
		gen_chan_info = ee->ee_pwr_cal_b;
		/* Fixed cal piers */
		gen_chan_info[0].freq = 2412;
		gen_chan_info[1].freq = 2447;
		gen_chan_info[2].freq = 2484;
		ee->ee_cal_piers_b = 3;
		cal_piers = ee->ee_cal_piers_b;