📄 app_vect_v5.lst
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\ 00000080 ............ DC32 BSP_IntHandlerDMA1_CH6, BSP_IntHandlerDMA1_CH7
\ ....
\ 00000088 ............ DC32 BSP_IntHandlerADC1_2, BSP_IntHandlerUSB_HP_CAN_TX
\ ....
\ 00000090 ............ DC32 BSP_IntHandlerUSB_LP_CAN_RX0, BSP_IntHandlerCAN_RX1
\ ....
\ 00000098 ............ DC32 BSP_IntHandlerCAN_SCE, BSP_IntHandlerEXTI9_5
\ ....
\ 000000A0 ............ DC32 BSP_IntHandlerTIM1_BRK, BSP_IntHandlerTIM1_UP
\ ....
\ 000000A8 ............ DC32 BSP_IntHandlerTIM1_TRG_COM, BSP_IntHandlerTIM1_CC
\ ....
\ 000000B0 ............ DC32 BSP_IntHandlerTIM2, BSP_IntHandlerTIM3, BSP_IntHandlerTIM4
\ ............
\ 000000BC ............ DC32 BSP_IntHandlerI2C1_EV, BSP_IntHandlerI2C1_ER
\ ....
\ 000000C4 ............ DC32 BSP_IntHandlerI2C2_EV, BSP_IntHandlerI2C2_ER, BSP_IntHandlerSPI1
\ ............
\ 000000D0 ............ DC32 BSP_IntHandlerSPI2, BSP_IntHandlerUSART1, BSP_IntHandlerUSART2
\ ............
\ 000000DC ............ DC32 BSP_IntHandlerUSART3, BSP_IntHandlerEXTI15_10
\ ....
\ 000000E4 ............ DC32 BSP_IntHandlerRTCAlarm, BSP_IntHandlerUSBWakeUp
\ ....
\ 000000EC ............ DC32 BSP_IntHandlerTIM8_BRK, BSP_IntHandlerTIM8_UP
\ ....
\ 000000F4 ............ DC32 BSP_IntHandlerTIM8_TRG_COM, BSP_IntHandlerTIM8_CC
\ ....
\ 000000FC ............ DC32 BSP_IntHandlerADC3, BSP_IntHandlerFSMC, BSP_IntHandlerSDIO
\ ............
\ 00000108 ............ DC32 BSP_IntHandlerTIM5, BSP_IntHandlerSPI3, BSP_IntHandlerUART4
\ ............
\ 00000114 ............ DC32 BSP_IntHandlerUART5, BSP_IntHandlerTIM6, BSP_IntHandlerTIM7
\ ............
\ 00000120 ............ DC32 BSP_IntHandlerDMA2_CH1, BSP_IntHandlerDMA2_CH2
\ ....
\ 00000128 ............ DC32 BSP_IntHandlerDMA2_CH3, BSP_IntHandlerDMA2_CH4_5
\ ....
107 { .Ptr = (void *)__sfe( "CSTACK" )}, /* 0, SP start value. */
108 //__iar_program_start, /* 1, PC start value. */
109 __program_start,
110 App_NMI_ISR, /* 2, NMI. */
111 App_Fault_ISR, /* 3, Hard Fault. */
112 App_MemFault_ISR, /* 4, Memory Management. */
113 App_BusFault_ISR, /* 5, Bus Fault. */
114 App_UsageFault_ISR, /* 6, Usage Fault. */
115 App_Spurious_ISR, /* 7, Reserved. */
116 App_Spurious_ISR, /* 8, Reserved. */
117 App_Spurious_ISR, /* 9, Reserved. */
118 App_Spurious_ISR, /* 10, Reserved. */
119 App_Spurious_ISR, /* 11, SVCall. */
120 App_Spurious_ISR, /* 12, Debug Monitor. */
121 App_Spurious_ISR, /* 13, Reserved. */
122 OS_CPU_PendSVHandler, /* 14, PendSV Handler. */
123 OS_CPU_SysTickHandler, /* 15, uC/OS-II Tick ISR Handler. */
124
125 BSP_IntHandlerWWDG, /* 16, INTISR[ 0] Window Watchdog. */
126 BSP_IntHandlerPVD, /* 17, INTISR[ 1] PVD through EXTI Line Detection. */
127 BSP_IntHandlerTAMPER, /* 18, INTISR[ 2] Tamper Interrupt. */
128 BSP_IntHandlerRTC, /* 19, INTISR[ 3] RTC Global Interrupt. */
129 BSP_IntHandlerFLASH, /* 20, INTISR[ 4] FLASH Global Interrupt. */
130 BSP_IntHandlerRCC, /* 21, INTISR[ 5] RCC Global Interrupt. */
131 BSP_IntHandlerEXTI0, /* 22, INTISR[ 6] EXTI Line0 Interrupt. */
132 BSP_IntHandlerEXTI1, /* 23, INTISR[ 7] EXTI Line1 Interrupt. */
133 BSP_IntHandlerEXTI2, /* 24, INTISR[ 8] EXTI Line2 Interrupt. */
134 BSP_IntHandlerEXTI3, /* 25, INTISR[ 9] EXTI Line3 Interrupt. */
135 BSP_IntHandlerEXTI4, /* 26, INTISR[ 10] EXTI Line4 Interrupt. */
136 BSP_IntHandlerDMA1_CH1, /* 27, INTISR[ 11] DMA Channel1 Global Interrupt. */
137 BSP_IntHandlerDMA1_CH2, /* 28, INTISR[ 12] DMA Channel2 Global Interrupt. */
138 BSP_IntHandlerDMA1_CH3, /* 29, INTISR[ 13] DMA Channel3 Global Interrupt. */
139 BSP_IntHandlerDMA1_CH4, /* 30, INTISR[ 14] DMA Channel4 Global Interrupt. */
140 BSP_IntHandlerDMA1_CH5, /* 31, INTISR[ 15] DMA Channel5 Global Interrupt. */
141
142 BSP_IntHandlerDMA1_CH6, /* 32, INTISR[ 16] DMA Channel6 Global Interrupt. */
143 BSP_IntHandlerDMA1_CH7, /* 33, INTISR[ 17] DMA Channel7 Global Interrupt. */
144 BSP_IntHandlerADC1_2, /* 34, INTISR[ 18] ADC1 & ADC2 Global Interrupt. */
145 BSP_IntHandlerUSB_HP_CAN_TX, /* 35, INTISR[ 19] USB High Prio / CAN TX Interrupts. */
146 BSP_IntHandlerUSB_LP_CAN_RX0, /* 36, INTISR[ 20] USB Low Prio / CAN RX0 Interrupts. */
147 BSP_IntHandlerCAN_RX1, /* 37, INTISR[ 21] CAN RX1 Interrupt. */
148 BSP_IntHandlerCAN_SCE, /* 38, INTISR[ 22] CAN SCE Interrupt. */
149 BSP_IntHandlerEXTI9_5, /* 39, INTISR[ 23] EXTI Line[9:5] Interrupt. */
150 BSP_IntHandlerTIM1_BRK, /* 40, INTISR[ 24] TIM1 Break Interrupt. */
151 BSP_IntHandlerTIM1_UP, /* 41, INTISR[ 25] TIM1 Update Interrupt. */
152 BSP_IntHandlerTIM1_TRG_COM, /* 42, INTISR[ 26] TIM1 Trig & Commutation Interrupts. */
153 BSP_IntHandlerTIM1_CC, /* 43, INTISR[ 27] TIM1 Capture Compare Interrupt. */
154 BSP_IntHandlerTIM2, /* 44, INTISR[ 28] TIM2 Global Interrupt. */
155 BSP_IntHandlerTIM3, /* 45, INTISR[ 29] TIM3 Global Interrupt. */
156 BSP_IntHandlerTIM4, /* 46, INTISR[ 30] TIM4 Global Interrupt. */
157 BSP_IntHandlerI2C1_EV, /* 47, INTISR[ 31] I2C1 Event Interrupt. */
158
159 BSP_IntHandlerI2C1_ER, /* 48, INTISR[ 32] I2C1 Error Interrupt. */
160 BSP_IntHandlerI2C2_EV, /* 49, INTISR[ 33] I2C2 Event Interrupt. */
161 BSP_IntHandlerI2C2_ER, /* 50, INTISR[ 34] I2C2 Error Interrupt. */
162 BSP_IntHandlerSPI1, /* 51, INTISR[ 35] SPI1 Global Interrupt. */
163 BSP_IntHandlerSPI2, /* 52, INTISR[ 36] SPI2 Global Interrupt. */
164 BSP_IntHandlerUSART1, /* 53, INTISR[ 37] USART1 Global Interrupt. */
165 BSP_IntHandlerUSART2, /* 54, INTISR[ 38] USART2 Global Interrupt. */
166 BSP_IntHandlerUSART3, /* 55, INTISR[ 39] USART3 Global Interrupt. */
167 BSP_IntHandlerEXTI15_10, /* 56, INTISR[ 40] EXTI Line [15:10] Interrupts. */
168 BSP_IntHandlerRTCAlarm, /* 57, INTISR[ 41] RTC Alarm EXT Line Interrupt. */
169 BSP_IntHandlerUSBWakeUp, /* 58, INTISR[ 42] USB Wakeup from Suspend EXTI Int. */
170 BSP_IntHandlerTIM8_BRK, /* 59, INTISR[ 43] TIM8 Break Interrupt. */
171 BSP_IntHandlerTIM8_UP, /* 60, INTISR[ 44] TIM8 Update Interrupt. */
172 BSP_IntHandlerTIM8_TRG_COM, /* 61, INTISR[ 45] TIM8 Trigg/Commutation Interrupts. */
173 BSP_IntHandlerTIM8_CC, /* 62, INTISR[ 46] TIM8 Capture Compare Interrupt. */
174 BSP_IntHandlerADC3, /* 63, INTISR[ 47] ADC3 Global Interrupt. */
175
176 BSP_IntHandlerFSMC, /* 64, INTISR[ 48] FSMC Global Interrupt. */
177 BSP_IntHandlerSDIO, /* 65, INTISR[ 49] SDIO Global Interrupt. */
178 BSP_IntHandlerTIM5, /* 66, INTISR[ 50] TIM5 Global Interrupt. */
179 BSP_IntHandlerSPI3, /* 67, INTISR[ 51] SPI3 Global Interrupt. */
180 BSP_IntHandlerUART4, /* 68, INTISR[ 52] UART4 Global Interrupt. */
181 BSP_IntHandlerUART5, /* 69, INTISR[ 53] UART5 Global Interrupt. */
182 BSP_IntHandlerTIM6, /* 70, INTISR[ 54] TIM6 Global Interrupt. */
183 BSP_IntHandlerTIM7, /* 71, INTISR[ 55] TIM7 Global Interrupt. */
184 BSP_IntHandlerDMA2_CH1, /* 72, INTISR[ 56] DMA2 Channel1 Global Interrupt. */
185 BSP_IntHandlerDMA2_CH2, /* 73, INTISR[ 57] DMA2 Channel2 Global Interrupt. */
186 BSP_IntHandlerDMA2_CH3, /* 74, INTISR[ 58] DMA2 Channel3 Global Interrupt. */
187 BSP_IntHandlerDMA2_CH4_5, /* 75, INTISR[ 59] DMA2 Channel4/5 Global Interrups. */
188 };
189
190 /*
191 *********************************************************************************************************
192 * __low_level_init()
193 *
194 * Description : Perform low-level initialization.
195 *
196 * Argument(s) : none.
197 *
198 * Return(s) : none.
199 *
200 * Caller(s) : IAR startup code.
201 *
202 * Note(s) : none.
203 *********************************************************************************************************
204 */
205 #ifdef STM32_EXT_SRAM
206 #pragma location="ICODE"
207 __interwork int __low_level_init(void)
208 {
209
210 /* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL */
211 /* if another Bank is req'd, adjust the Reg Addrs */
212
213 *(volatile CPU_INT32U *)0x40021014 = 0x00000114; /* Enable FSMC clock */
214
215
216 *(volatile CPU_INT32U *)0x40021018 = 0x000001E0; /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
217
218
219 /* --------------------- CFG GPIO --------------------- */
220 /* SRAM Data lines, NOE and NWE configuration */
221 /* SRAM Address lines configuration */
222 /* NOE and NWE configuration */
223 /* NE3 configuration */
224 /* NBL0, NBL1 configuration */
225 *(volatile CPU_INT32U *)0x40011400 = 0x44BB44BB;
226 *(volatile CPU_INT32U *)0x40011404 = 0xBBBBBBBB;
227
228 *(volatile CPU_INT32U *)0x40011800 = 0xB44444BB;
229 *(volatile CPU_INT32U *)0x40011804 = 0xBBBBBBBB;
230
231 *(volatile CPU_INT32U *)0x40011C00 = 0x44BBBBBB;
232 *(volatile CPU_INT32U *)0x40011C04 = 0xBBBB4444;
233
234 *(volatile CPU_INT32U *)0x40012000 = 0x44BBBBBB;
235 *(volatile CPU_INT32U *)0x40012004 = 0x44444B44;
236
237
238 /* --------------------- CFG FSMC --------------------- */
239 *(volatile CPU_INT32U *)0xA0000010 = 0x00001011; /* Enable FSMC Bank1_SRAM Bank */
240 *(volatile CPU_INT32U *)0xA0000014 = 0x00000200;
241
242 return (1);
243 }
244 #endif
245
246 /*
247 *********************************************************************************************************
248 * App_NMI_ISR()
249 *
250 * Description : Handle Non-Maskable Interrupt (NMI).
251 *
252 * Argument(s) : none.
253 *
254 * Return(s) : none.
255 *
256 * Caller(s) : This is an ISR.
257 *
258 * Note(s) : (1) Since the NMI is not being used, this serves merely as a catch for a spurious
259 * exception.
260 *********************************************************************************************************
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