📄 stm32f10x_adc.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 KICKSTART 26/Dec/2008 18:22:05 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Stack alignment = 4 #
# Source file = F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_a #
# dc.c #
# Command line = F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_a #
# dc.c -lCN F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3 #
# 210E-EVAL\IAR\OS-Probe\Flash\List\ -o #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\Obj\ -z6 --no_unroll --no_inline #
# --no_tbaa --no_scheduling --debug --cpu_mode thumb #
# --endian little --cpu cortex-M3 --stack_align 4 -e #
# --fpu None --dlib_config "E:\Program Files\IAR #
# Systems\Embedded Workbench 4.0 #
# Kickstart\arm\LIB\dl7mptnnl8n.h" -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ #
# ST\STM3210E-EVAL\IAR\OS-Probe\..\BSP\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\CPU\ST\STM32\inc\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-CPU\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-CPU\ARM-Cortex-M3\IAR #
# \ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E- #
# EVAL\IAR\OS-Probe\..\..\..\..\..\uC-LCD\Source\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-LIB\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uCOS-II\Ports\ARM-Cortex #
# -M3\Generic\IAR\ -I F:\PROJECT\STM32_UCOSII\EvalBoar #
# ds\ST\STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\..\uCOS #
# -II\Source\ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ST #
# \STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\..\uC-Probe\ #
# Target\Communication\Generic\RS-232\Source\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-Probe\Target\Communic #
# ation\Generic\RS-232\Ports\ST\STM32\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-Probe\Target\Communic #
# ation\Generic\Source\ -I F:\PROJECT\STM32_UCOSII\Eva #
# lBoards\ST\STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\.. #
# \uC-Probe\Target\Plugins\uCOS-II\ -I "E:\Program #
# Files\IAR Systems\Embedded Workbench 4.0 #
# Kickstart\arm\INC\" #
# List file = F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\List\stm32f10x_adc.lst #
# Object file = F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\Obj\stm32f10x_adc.r79 #
# #
# #
##############################################################################
F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_adc.c
1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2 * File Name : stm32f10x_adc.c
3 * Author : MCD Application Team
4 * Version : V2.0
5 * Date : 05/23/2008
6 * Description : This file provides all the ADC firmware functions.
7 ********************************************************************************
8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
15 * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
16 *******************************************************************************/
17
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32f10x_adc.h"
20 #include "stm32f10x_rcc.h"
21
22 /* Private typedef -----------------------------------------------------------*/
23 /* Private define ------------------------------------------------------------*/
24 /* ADC DISCNUM mask */
25 #define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF)
26
27 /* ADC DISCEN mask */
28 #define CR1_DISCEN_Set ((u32)0x00000800)
29 #define CR1_DISCEN_Reset ((u32)0xFFFFF7FF)
30
31 /* ADC JAUTO mask */
32 #define CR1_JAUTO_Set ((u32)0x00000400)
33 #define CR1_JAUTO_Reset ((u32)0xFFFFFBFF)
34
35 /* ADC JDISCEN mask */
36 #define CR1_JDISCEN_Set ((u32)0x00001000)
37 #define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF)
38
39 /* ADC AWDCH mask */
40 #define CR1_AWDCH_Reset ((u32)0xFFFFFFE0)
41
42 /* ADC Analog watchdog enable mode mask */
43 #define CR1_AWDMode_Reset ((u32)0xFF3FFDFF)
44
45 /* CR1 register Mask */
46 #define CR1_CLEAR_Mask ((u32)0xFFF0FEFF)
47
48 /* ADC ADON mask */
49 #define CR2_ADON_Set ((u32)0x00000001)
50 #define CR2_ADON_Reset ((u32)0xFFFFFFFE)
51
52 /* ADC DMA mask */
53 #define CR2_DMA_Set ((u32)0x00000100)
54 #define CR2_DMA_Reset ((u32)0xFFFFFEFF)
55
56 /* ADC RSTCAL mask */
57 #define CR2_RSTCAL_Set ((u32)0x00000008)
58
59 /* ADC CAL mask */
60 #define CR2_CAL_Set ((u32)0x00000004)
61
62 /* ADC SWSTART mask */
63 #define CR2_SWSTART_Set ((u32)0x00400000)
64
65 /* ADC EXTTRIG mask */
66 #define CR2_EXTTRIG_Set ((u32)0x00100000)
67 #define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF)
68
69 /* ADC Software start mask */
70 #define CR2_EXTTRIG_SWSTART_Set ((u32)0x00500000)
71 #define CR2_EXTTRIG_SWSTART_Reset ((u32)0xFFAFFFFF)
72
73 /* ADC JEXTSEL mask */
74 #define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF)
75
76 /* ADC JEXTTRIG mask */
77 #define CR2_JEXTTRIG_Set ((u32)0x00008000)
78 #define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF)
79
80 /* ADC JSWSTART mask */
81 #define CR2_JSWSTART_Set ((u32)0x00200000)
82
83 /* ADC injected software start mask */
84 #define CR2_JEXTTRIG_JSWSTART_Set ((u32)0x00208000)
85 #define CR2_JEXTTRIG_JSWSTART_Reset ((u32)0xFFDF7FFF)
86
87 /* ADC TSPD mask */
88 #define CR2_TSVREFE_Set ((u32)0x00800000)
89 #define CR2_TSVREFE_Reset ((u32)0xFF7FFFFF)
90
91 /* CR2 register Mask */
92 #define CR2_CLEAR_Mask ((u32)0xFFF1F7FD)
93
94 /* ADC SQx mask */
95 #define SQR3_SQ_Set ((u32)0x0000001F)
96 #define SQR2_SQ_Set ((u32)0x0000001F)
97 #define SQR1_SQ_Set ((u32)0x0000001F)
98
99 /* SQR1 register Mask */
100 #define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF)
101
102 /* ADC JSQx mask */
103 #define JSQR_JSQ_Set ((u32)0x0000001F)
104
105 /* ADC JL mask */
106 #define JSQR_JL_Set ((u32)0x00300000)
107 #define JSQR_JL_Reset ((u32)0xFFCFFFFF)
108
109 /* ADC SMPx mask */
110 #define SMPR1_SMP_Set ((u32)0x00000007)
111 #define SMPR2_SMP_Set ((u32)0x00000007)
112
113 /* ADC JDRx registers offset */
114 #define JDR_Offset ((u8)0x28)
115
116 /* ADC1 DR register base address */
117 #define DR_ADDRESS ((u32)0x4001244C)
118
119 /* Private macro -------------------------------------------------------------*/
120 /* Private variables ---------------------------------------------------------*/
121 /* Private function prototypes -----------------------------------------------*/
122 /* Private functions ---------------------------------------------------------*/
123
124 /*******************************************************************************
125 * Function Name : ADC_DeInit
126 * Description : Deinitializes the ADCx peripheral registers to their default
127 * reset values.
128 * Input : - ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
129 * Output : None
130 * Return : None
131 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
132 void ADC_DeInit(ADC_TypeDef* ADCx)
133 {
\ ADC_DeInit:
\ 00000000 00B5 PUSH {LR}
134 /* Check the parameters */
135 assert_param(IS_ADC_ALL_PERIPH(ADCx));
136
137 switch (*(u32*)&ADCx)
\ 00000002 1449 LDR.N R1,??ADC_DeInit_0 ;; 0x40012400
\ 00000004 8842 CMP R0,R1
\ 00000006 06D0 BEQ.N ??ADC_DeInit_1
\ 00000008 1349 LDR.N R1,??ADC_DeInit_0+0x4 ;; 0x40012800
\ 0000000A 8842 CMP R0,R1
\ 0000000C 0DD0 BEQ.N ??ADC_DeInit_2
\ 0000000E 1349 LDR.N R1,??ADC_DeInit_0+0x8 ;; 0x40013c00
\ 00000010 8842 CMP R0,R1
\ 00000012 14D0 BEQ.N ??ADC_DeInit_3
\ 00000014 00BD POP {PC}
138 {
139 case ADC1_BASE:
140 /* Enable ADC1 reset state */
141 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
\ ??ADC_DeInit_1:
\ 00000016 0121 MOVS R1,#+1
\ 00000018 4802 LSLS R0,R1,#+9
\ 0000001A ........ _BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
142 /* Release ADC1 from reset state */
143 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
\ 0000001E 0021 MOVS R1,#+0
\ 00000020 5FF40070 MOVS R0,#+512
\ 00000024 ........ _BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
\ 00000028 00BD POP {PC}
144 break;
145
146 case ADC2_BASE:
147 /* Enable ADC2 reset state */
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