📄 stm32f10x_sdio.lst
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127 * Output : None
128 * Return : None
129 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
130 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
131 {
132 u32 tmpreg = 0;
133
134 /* Check the parameters */
135 assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
136 assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
137 assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
138 assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
139 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
140
141 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
142 /* Get the SDIO CLKCR value */
143 tmpreg = SDIO->CLKCR;
\ SDIO_Init:
\ 00000000 0849 LDR.N R1,??SDIO_Init_0 ;; 0x40018004
\ 00000002 0A68 LDR R2,[R1, #+0]
144
145 /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
146 tmpreg &= CLKCR_CLEAR_MASK;
147
148 /* Set CLKDIV bits according to SDIO_ClockDiv value */
149 /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
150 /* Set BYPASS bit according to SDIO_ClockBypass value */
151 /* Set WIDBUS bits according to SDIO_BusWide value */
152 /* Set NEGEDGE bits according to SDIO_ClockEdge value */
153 /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
154 tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
155 SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
156 SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
157
158 /* Write to SDIO CLKCR */
159 SDIO->CLKCR = tmpreg;
\ 00000004 084B LDR.N R3,??SDIO_Init_0+0x4 ;; 0xffffffffffff8100
\ 00000006 1340 ANDS R3,R3,R2
\ 00000008 0278 LDRB R2,[R0, #+0]
\ 0000000A 1A43 ORRS R2,R2,R3
\ 0000000C C368 LDR R3,[R0, #+12]
\ 0000000E 1343 ORRS R3,R3,R2
\ 00000010 8268 LDR R2,[R0, #+8]
\ 00000012 1A43 ORRS R2,R2,R3
\ 00000014 0369 LDR R3,[R0, #+16]
\ 00000016 1343 ORRS R3,R3,R2
\ 00000018 4268 LDR R2,[R0, #+4]
\ 0000001A 1A43 ORRS R2,R2,R3
\ 0000001C 4069 LDR R0,[R0, #+20]
\ 0000001E 1043 ORRS R0,R0,R2
\ 00000020 0860 STR R0,[R1, #+0]
160 }
\ 00000022 7047 BX LR ;; return
\ ??SDIO_Init_0:
\ 00000024 04800140 DC32 0x40018004
\ 00000028 0081FFFF DC32 0xffffffffffff8100
161
162 /*******************************************************************************
163 * Function Name : SDIO_StructInit
164 * Description : Fills each SDIO_InitStruct member with its default value.
165 * Input : SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
166 * will be initialized.
167 * Output : None
168 * Return : None
169 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
170 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
171 {
172 /* SDIO_InitStruct members default value */
173 SDIO_InitStruct->SDIO_ClockDiv = 0x00;
\ SDIO_StructInit:
\ 00000000 0021 MOVS R1,#+0
\ 00000002 0A00 MOVS R2,R1
\ 00000004 0270 STRB R2,[R0, #+0]
174 SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
\ 00000006 4160 STR R1,[R0, #+4]
175 SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
\ 00000008 8160 STR R1,[R0, #+8]
176 SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
\ 0000000A C160 STR R1,[R0, #+12]
177 SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
\ 0000000C 0161 STR R1,[R0, #+16]
178 SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
\ 0000000E 4161 STR R1,[R0, #+20]
179 }
\ 00000010 7047 BX LR ;; return
180
181 /*******************************************************************************
182 * Function Name : SDIO_ClockCmd
183 * Description : Enables or disables the SDIO Clock.
184 * Input : NewState: new state of the SDIO Clock.
185 * This parameter can be: ENABLE or DISABLE.
186 * Output : None
187 * Return : None
188 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
189 void SDIO_ClockCmd(FunctionalState NewState)
190 {
191 /* Check the parameters */
192 assert_param(IS_FUNCTIONAL_STATE(NewState));
193
194 *(vu32 *) CLKCR_CLKEN_BB = (u32)NewState;
\ SDIO_ClockCmd:
\ 00000000 0149 LDR.N R1,??SDIO_ClockCmd_0 ;; 0x423000a0
\ 00000002 0860 STR R0,[R1, #+0]
195 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??SDIO_ClockCmd_0:
\ 00000008 A0003042 DC32 0x423000a0
196
197 /*******************************************************************************
198 * Function Name : SDIO_SetPowerState
199 * Description : Sets the power status of the controller.
200 * Input : SDIO_PowerState: new state of the Power state.
201 * This parameter can be one of the following values:
202 * - SDIO_PowerState_OFF
203 * - SDIO_PowerState_ON
204 * Output : None
205 * Return : None
206 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
207 void SDIO_SetPowerState(u32 SDIO_PowerState)
208 {
209 /* Check the parameters */
210 assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
211
212 SDIO->POWER &= PWR_PWRCTRL_MASK;
\ SDIO_SetPowerState:
\ 00000000 .... LDR.N R1,??DataTable2 ;; 0x40018000
\ 00000002 0A68 LDR R2,[R1, #+0]
\ 00000004 0323 MOVS R3,#+3
\ 00000006 9A43 BICS R2,R2,R3
\ 00000008 0A60 STR R2,[R1, #+0]
213 SDIO->POWER |= SDIO_PowerState;
\ 0000000A 0A68 LDR R2,[R1, #+0]
\ 0000000C 1043 ORRS R0,R0,R2
\ 0000000E 0860 STR R0,[R1, #+0]
214 }
\ 00000010 7047 BX LR ;; return
215
216 /*******************************************************************************
217 * Function Name : SDIO_GetPowerState
218 * Description : Gets the power status of the controller.
219 * Input : None
220 * Output : None
221 * Return : Power status of the controller. The returned value can
222 * be one of the following:
223 * - 0x00: Power OFF
224 * - 0x02: Power UP
225 * - 0x03: Power ON
226 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
227 u32 SDIO_GetPowerState(void)
228 {
229 return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
\ SDIO_GetPowerState:
\ 00000000 .... LDR.N R0,??DataTable2 ;; 0x40018000
\ 00000002 0068 LDR R0,[R0, #+0]
\ 00000004 8007 LSLS R0,R0,#+30
\ 00000006 800F LSRS R0,R0,#+30
\ 00000008 7047 BX LR ;; return
230 }
231
232 /*******************************************************************************
233 * Function Name : SDIO_ITConfig
234 * Description : Enables or disables the SDIO interrupts.
235 * Input : - SDIO_IT: specifies the SDIO interrupt sources to be
236 * enabled or disabled.
237 * This parameter can be one or a combination of the following
238 * values:
239 * - SDIO_IT_CCRCFAIL: Command response received (CRC check
240 * failed) interrupt
241 * - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
242 * failed) interrupt
243 * - SDIO_IT_CTIMEOUT: Command response timeout interrupt
244 * - SDIO_IT_DTIMEOUT: Data timeout interrupt
245 * - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
246 * - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
247 * - SDIO_IT_CMDREND: Command response received (CRC check
248 * passed) interrupt
249 * - SDIO_IT_CMDSENT: Command sent (no response required)
250 * interrupt
251 * - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
252 * zero) interrupt
253 * - SDIO_IT_STBITERR: Start bit not detected on all data
254 * signals in wide bus mode interrupt
255 * - SDIO_IT_DBCKEND: Data block sent/received (CRC check
256 * passed) interrupt
257 * - SDIO_IT_CMDACT: Command transfer in progress interrupt
258 * - SDIO_IT_TXACT: Data transmit in progress interrupt
259 * - SDIO_IT_RXACT: Data receive in progress interrupt
260 * - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
261 * - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
262 * - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
263 * - SDIO_IT_RXFIFOF: Receive FIFO full interrupt
264 * - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
265 * - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
266 * - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
267 * - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
268 * - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
269 * - SDIO_IT_CEATAEND: CE-ATA command completion signal
270 * received for CMD61 interrupt
271 * - NewState: new state of the specified SDIO interrupts.
272 * This parameter can be: ENABLE or DISABLE.
273 * Output : None
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