📄 stm32f10x_rcc.lst
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613 {
614 /* Check the parameters */
615 assert_param(IS_FUNCTIONAL_STATE(NewState));
616
617 *(vu32 *) CSR_LSION_BB = (u32)NewState;
\ RCC_LSICmd:
\ 00000000 0149 LDR.N R1,??RCC_LSICmd_0 ;; 0x42420480
\ 00000002 0860 STR R0,[R1, #+0]
618 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_LSICmd_0:
\ 00000008 80044242 DC32 0x42420480
619
620 /*******************************************************************************
621 * Function Name : RCC_RTCCLKConfig
622 * Description : Configures the RTC clock (RTCCLK).
623 * Once the RTC clock is selected it can抰 be changed unless the
624 * Backup domain is reset.
625 * Input : - RCC_RTCCLKSource: specifies the RTC clock source.
626 * This parameter can be one of the following values:
627 * - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
628 * - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
629 * - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
630 * selected as RTC clock
631 * Output : None
632 * Return : None
633 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
634 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
635 {
636 /* Check the parameters */
637 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
638
639 /* Select the RTC clock source */
640 RCC->BDCR |= RCC_RTCCLKSource;
\ RCC_RTCCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable16 ;; 0x40021020
\ 00000002 0A68 LDR R2,[R1, #+0]
\ 00000004 1043 ORRS R0,R0,R2
\ 00000006 0860 STR R0,[R1, #+0]
641 }
\ 00000008 7047 BX LR ;; return
642
643 /*******************************************************************************
644 * Function Name : RCC_RTCCLKCmd
645 * Description : Enables or disables the RTC clock.
646 * This function must be used only after the RTC clock was
647 * selected using the RCC_RTCCLKConfig function.
648 * Input : - NewState: new state of the RTC clock.
649 * This parameter can be: ENABLE or DISABLE.
650 * Output : None
651 * Return : None
652 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
653 void RCC_RTCCLKCmd(FunctionalState NewState)
654 {
655 /* Check the parameters */
656 assert_param(IS_FUNCTIONAL_STATE(NewState));
657
658 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
\ RCC_RTCCLKCmd:
\ 00000000 0149 LDR.N R1,??RCC_RTCCLKCmd_0 ;; 0x4242043c
\ 00000002 0860 STR R0,[R1, #+0]
659 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_RTCCLKCmd_0:
\ 00000008 3C044242 DC32 0x4242043c
660
661 /*******************************************************************************
662 * Function Name : RCC_GetClocksFreq
663 * Description : Returns the frequencies of different on chip clocks.
664 * Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
665 * will hold the clocks frequencies.
666 * Output : None
667 * Return : None
668 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
669 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
670 {
\ RCC_GetClocksFreq:
\ 00000000 30B5 PUSH {R4,R5,LR}
671 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
672
673 /* Get SYSCLK source -------------------------------------------------------*/
674 tmp = RCC->CFGR & CFGR_SWS_Mask;
\ 00000002 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000004 0A68 LDR R2,[R1, #+0]
\ 00000006 12F00C03 ANDS R3,R2,#0xC
675
676 switch (tmp)
\ 0000000A 204A LDR.N R2,??RCC_GetClocksFreq_0 ;; 0x7a1200
\ 0000000C 082B CMP R3,#+8
\ 0000000E 01D0 BEQ.N ??RCC_GetClocksFreq_1
677 {
678 case 0x00: /* HSI used as system clock */
679 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\ 00000010 0260 STR R2,[R0, #+0]
\ 00000012 16E0 B.N ??RCC_GetClocksFreq_2
680 break;
681
682 case 0x04: /* HSE used as system clock */
683 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
684 break;
685
686 case 0x08: /* PLL used as system clock */
687 /* Get PLL clock source and multiplication factor ----------------------*/
688 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
\ ??RCC_GetClocksFreq_1:
\ 00000014 0B68 LDR R3,[R1, #+0]
\ 00000016 13F47013 ANDS R3,R3,#0x3C0000
689 pllmull = ( pllmull >> 18) + 2;
\ 0000001A 9B0C LSRS R3,R3,#+18
\ 0000001C 9B1C ADDS R3,R3,#+2
690
691 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
\ 0000001E 0D68 LDR R5,[R1, #+0]
\ 00000020 5FF48034 MOVS R4,#+65536
\ 00000024 2C40 ANDS R4,R4,R5
692
693 if (pllsource == 0x00)
\ 00000026 03D1 BNE.N ??RCC_GetClocksFreq_3
694 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
695 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
\ 00000028 5208 LSRS R2,R2,#+1
\ 0000002A 5343 MULS R3,R2,R3
\ 0000002C 0360 STR R3,[R0, #+0]
\ 0000002E 08E0 B.N ??RCC_GetClocksFreq_2
696 }
697 else
698 {/* HSE selected as PLL clock entry */
699
700 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
\ ??RCC_GetClocksFreq_3:
\ 00000030 0C68 LDR R4,[R1, #+0]
\ 00000032 A403 LSLS R4,R4,#+14
\ 00000034 03D5 BPL.N ??RCC_GetClocksFreq_4
701 {/* HSE oscillator clock divided by 2 */
702
703 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
\ 00000036 5208 LSRS R2,R2,#+1
\ 00000038 5343 MULS R3,R2,R3
\ 0000003A 0360 STR R3,[R0, #+0]
\ 0000003C 01E0 B.N ??RCC_GetClocksFreq_2
704 }
705 else
706 {
707 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
\ ??RCC_GetClocksFreq_4:
\ 0000003E 5343 MULS R3,R2,R3
\ 00000040 0360 STR R3,[R0, #+0]
708 }
709 }
710 break;
711
712 default:
713 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
714 break;
715 }
716
717 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
718 /* Get HCLK prescaler */
719 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
\ ??RCC_GetClocksFreq_2:
\ 00000042 0A68 LDR R2,[R1, #+0]
\ 00000044 12F0F003 ANDS R3,R2,#0xF0
720 tmp = tmp >> 4;
721 presc = APBAHBPrescTable[tmp];
722
723 /* HCLK clock frequency */
724 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
\ 00000048 114A LDR.N R2,??RCC_GetClocksFreq_0+0x4 ;; APBAHBPrescTable
\ 0000004A 0468 LDR R4,[R0, #+0]
\ 0000004C 1B09 LSRS R3,R3,#+4
\ 0000004E D35C LDRB R3,[R2, R3]
\ 00000050 DC40 LSRS R4,R4,R3
\ 00000052 4460 STR R4,[R0, #+4]
725
726 /* Get PCLK1 prescaler */
727 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
\ 00000054 0B68 LDR R3,[R1, #+0]
\ 00000056 13F4E063 ANDS R3,R3,#0x700
728 tmp = tmp >> 8;
729 presc = APBAHBPrescTable[tmp];
730
731 /* PCLK1 clock frequency */
732 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\ 0000005A 4468 LDR R4,[R0, #+4]
\ 0000005C 1B0A LSRS R3,R3,#+8
\ 0000005E D35C LDRB R3,[R2, R3]
\ 00000060 DC40 LSRS R4,R4,R3
\ 00000062 8460 STR R4,[R0, #+8]
733
734 /* Get PCLK2 prescaler */
735 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
\ 00000064 0B68 LDR R3,[R1, #+0]
\ 00000066 13F46053 ANDS R3,R3,#0x3800
736 tmp = tmp >> 11;
737 presc = APBAHBPrescTable[tmp];
738
739 /* PCLK2 clock frequency */
740 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\ 0000006A 4468 LDR R4,[R0, #+4]
\ 0000006C DB0A LSRS R3,R3,#+11
\ 0000006E D35C LDRB R3,[R2, R3]
\ 00000070 DC40 LSRS R4,R4,R3
\ 00000072 C460 STR R4,[R0, #+12]
741
742 /* Get ADCCLK prescaler */
743 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
\ 00000074 0968 LDR R1,[R1, #+0]
\ 00000076 11F44041 ANDS R1,R1,#0xC000
744 tmp = tmp >> 14;
745 presc = ADCPrescTable[tmp];
746
747 /* ADCCLK clock frequency */
748 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
\ 0000007A C368 LDR R3,[R0, #+12]
\ 0000007C 12EB9131 ADDS R1,R2,R1, LSR #+14
\ 00000080 097C LDRB R1,[R1, #+16]
\ 00000082 B3FBF1F1 UDIV R1,R3,R1
\ 00000086 0161 STR R1,[R0, #+16]
749 }
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