📄 stm32f10x_rcc.lst
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450 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
451 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
452 * Output : None
453 * Return : None
454 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
455 void RCC_PCLK2Config(u32 RCC_HCLK)
456 {
457 u32 tmpreg = 0;
458
459 /* Check the parameters */
460 assert_param(IS_RCC_PCLK(RCC_HCLK));
461
462 tmpreg = RCC->CFGR;
\ RCC_PCLK2Config:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
463
464 /* Clear PPRE2[2:0] bits */
465 tmpreg &= CFGR_PPRE2_Reset_Mask;
466
467 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
468 tmpreg |= RCC_HCLK << 3;
469
470 /* Store the new value */
471 RCC->CFGR = tmpreg;
\ 00000004 7FF46053 MVNS R3,#+14336
\ 00000008 1340 ANDS R3,R3,R2
\ 0000000A 53EAC000 ORRS R0,R3,R0, LSL #+3
\ 0000000E 0860 STR R0,[R1, #+0]
472 }
\ 00000010 7047 BX LR ;; return
473
474 /*******************************************************************************
475 * Function Name : RCC_ITConfig
476 * Description : Enables or disables the specified RCC interrupts.
477 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
478 * or disabled.
479 * This parameter can be any combination of the following values:
480 * - RCC_IT_LSIRDY: LSI ready interrupt
481 * - RCC_IT_LSERDY: LSE ready interrupt
482 * - RCC_IT_HSIRDY: HSI ready interrupt
483 * - RCC_IT_HSERDY: HSE ready interrupt
484 * - RCC_IT_PLLRDY: PLL ready interrupt
485 * - NewState: new state of the specified RCC interrupts.
486 * This parameter can be: ENABLE or DISABLE.
487 * Output : None
488 * Return : None
489 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
490 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
491 {
492 /* Check the parameters */
493 assert_param(IS_RCC_IT(RCC_IT));
494 assert_param(IS_FUNCTIONAL_STATE(NewState));
495
496 if (NewState != DISABLE)
\ RCC_ITConfig:
\ 00000000 044A LDR.N R2,??RCC_ITConfig_0 ;; 0x40021009
\ 00000002 0029 CMP R1,#+0
\ 00000004 1178 LDRB R1,[R2, #+0]
\ 00000006 02D0 BEQ.N ??RCC_ITConfig_1
497 {
498 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
499 *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
\ 00000008 0843 ORRS R0,R0,R1
\ 0000000A 1070 STRB R0,[R2, #+0]
\ 0000000C 7047 BX LR
500 }
501 else
502 {
503 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
504 *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
\ ??RCC_ITConfig_1:
\ 0000000E 8143 BICS R1,R1,R0
\ 00000010 1170 STRB R1,[R2, #+0]
505 }
506 }
\ 00000012 7047 BX LR ;; return
\ ??RCC_ITConfig_0:
\ 00000014 09100240 DC32 0x40021009
507
508 /*******************************************************************************
509 * Function Name : RCC_USBCLKConfig
510 * Description : Configures the USB clock (USBCLK).
511 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
512 * is derived from the PLL output.
513 * This parameter can be one of the following values:
514 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
515 * selected as USB clock source
516 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
517 * clock source
518 * Output : None
519 * Return : None
520 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
521 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
522 {
523 /* Check the parameters */
524 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
525
526 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
\ RCC_USBCLKConfig:
\ 00000000 0149 LDR.N R1,??RCC_USBCLKConfig_0 ;; 0x424200d8
\ 00000002 0860 STR R0,[R1, #+0]
527 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_USBCLKConfig_0:
\ 00000008 D8004242 DC32 0x424200d8
528
529 /*******************************************************************************
530 * Function Name : RCC_ADCCLKConfig
531 * Description : Configures the ADC clock (ADCCLK).
532 * Input : - RCC_PCLK2: defines the ADC clock divider. This clock is
533 * derived from the APB2 clock (PCLK2).
534 * This parameter can be one of the following values:
535 * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
536 * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
537 * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
538 * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
539 * Output : None
540 * Return : None
541 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
542 void RCC_ADCCLKConfig(u32 RCC_PCLK2)
543 {
544 u32 tmpreg = 0;
545
546 /* Check the parameters */
547 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
548
549 tmpreg = RCC->CFGR;
\ RCC_ADCCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
550
551 /* Clear ADCPRE[1:0] bits */
552 tmpreg &= CFGR_ADCPRE_Reset_Mask;
553
554 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
555 tmpreg |= RCC_PCLK2;
556
557 /* Store the new value */
558 RCC->CFGR = tmpreg;
\ 00000004 7FF44043 MVNS R3,#+49152
\ 00000008 1340 ANDS R3,R3,R2
\ 0000000A 1843 ORRS R0,R0,R3
\ 0000000C 0860 STR R0,[R1, #+0]
559 }
\ 0000000E 7047 BX LR ;; return
560
561 /*******************************************************************************
562 * Function Name : RCC_LSEConfig
563 * Description : Configures the External Low Speed oscillator (LSE).
564 * Input : - RCC_LSE: specifies the new state of the LSE.
565 * This parameter can be one of the following values:
566 * - RCC_LSE_OFF: LSE oscillator OFF
567 * - RCC_LSE_ON: LSE oscillator ON
568 * - RCC_LSE_Bypass: LSE oscillator bypassed with external
569 * clock
570 * Output : None
571 * Return : None
572 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
573 void RCC_LSEConfig(u8 RCC_LSE)
574 {
\ RCC_LSEConfig:
\ 00000000 00B5 PUSH {LR}
575 /* Check the parameters */
576 assert_param(IS_RCC_LSE(RCC_LSE));
577
578 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
579 /* Reset LSEON bit */
580 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
\ 00000002 .... LDR.N R1,??DataTable16 ;; 0x40021020
\ 00000004 0022 MOVS R2,#+0
\ 00000006 0A70 STRB R2,[R1, #+0]
581
582 /* Reset LSEBYP bit */
583 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
\ 00000008 0A70 STRB R2,[R1, #+0]
584
585 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
586 switch(RCC_LSE)
\ 0000000A 0128 CMP R0,#+1
\ 0000000C 02D0 BEQ.N ??RCC_LSEConfig_0
\ 0000000E 0428 CMP R0,#+4
\ 00000010 02D0 BEQ.N ??RCC_LSEConfig_1
\ 00000012 00BD POP {PC}
587 {
588 case RCC_LSE_ON:
589 /* Set LSEON bit */
590 *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
\ ??RCC_LSEConfig_0:
\ 00000014 0870 STRB R0,[R1, #+0]
\ 00000016 00BD POP {PC}
591 break;
592
593 case RCC_LSE_Bypass:
594 /* Set LSEBYP and LSEON bits */
595 *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
\ ??RCC_LSEConfig_1:
\ 00000018 0520 MOVS R0,#+5
\ 0000001A 0870 STRB R0,[R1, #+0]
596 break;
597
598 default:
599 break;
600 }
601 }
\ 0000001C 00BD POP {PC} ;; return
602
603 /*******************************************************************************
604 * Function Name : RCC_LSICmd
605 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
606 * LSI can not be disabled if the IWDG is running.
607 * Input : - NewState: new state of the LSI.
608 * This parameter can be: ENABLE or DISABLE.
609 * Output : None
610 * Return : None
611 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
612 void RCC_LSICmd(FunctionalState NewState)
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