📄 stm32f10x_rcc.lst
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278 * by 2 selected as PLL clock entry
279 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
280 * as PLL clock entry
281 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
282 * by 2 selected as PLL clock entry
283 * - RCC_PLLMul: specifies the PLL multiplication factor.
284 * This parameter can be RCC_PLLMul_x where x:[2,16]
285 * Output : None
286 * Return : None
287 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
288 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
289 {
\ RCC_PLLConfig:
\ 00000000 10B5 PUSH {R4,LR}
290 u32 tmpreg = 0;
291
292 /* Check the parameters */
293 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
294 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
295
296 tmpreg = RCC->CFGR;
\ 00000002 .... LDR.N R2,??DataTable14 ;; 0x40021004
\ 00000004 1368 LDR R3,[R2, #+0]
297
298 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
299 tmpreg &= CFGR_PLL_Mask;
300
301 /* Set the PLL configuration bits */
302 tmpreg |= RCC_PLLSource | RCC_PLLMul;
303
304 /* Store the new value */
305 RCC->CFGR = tmpreg;
\ 00000006 7FF47C14 MVNS R4,#+4128768
\ 0000000A 1C40 ANDS R4,R4,R3
\ 0000000C 2043 ORRS R0,R0,R4
\ 0000000E 0143 ORRS R1,R1,R0
\ 00000010 1160 STR R1,[R2, #+0]
306 }
\ 00000012 10BD POP {R4,PC} ;; return
307
308 /*******************************************************************************
309 * Function Name : RCC_PLLCmd
310 * Description : Enables or disables the PLL.
311 * The PLL can not be disabled if it is used as system clock.
312 * Input : - NewState: new state of the PLL.
313 * This parameter can be: ENABLE or DISABLE.
314 * Output : None
315 * Return : None
316 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
317 void RCC_PLLCmd(FunctionalState NewState)
318 {
319 /* Check the parameters */
320 assert_param(IS_FUNCTIONAL_STATE(NewState));
321
322 *(vu32 *) CR_PLLON_BB = (u32)NewState;
\ RCC_PLLCmd:
\ 00000000 0149 LDR.N R1,??RCC_PLLCmd_0 ;; 0x42420060
\ 00000002 0860 STR R0,[R1, #+0]
323 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_PLLCmd_0:
\ 00000008 60004242 DC32 0x42420060
324
325 /*******************************************************************************
326 * Function Name : RCC_SYSCLKConfig
327 * Description : Configures the system clock (SYSCLK).
328 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
329 * clock. This parameter can be one of the following values:
330 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
331 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
332 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
333 * Output : None
334 * Return : None
335 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
336 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
337 {
338 u32 tmpreg = 0;
339
340 /* Check the parameters */
341 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
342
343 tmpreg = RCC->CFGR;
\ RCC_SYSCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
344
345 /* Clear SW[1:0] bits */
346 tmpreg &= CFGR_SW_Mask;
347
348 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
349 tmpreg |= RCC_SYSCLKSource;
350
351 /* Store the new value */
352 RCC->CFGR = tmpreg;
\ 00000004 0323 MOVS R3,#+3
\ 00000006 9A43 BICS R2,R2,R3
\ 00000008 1043 ORRS R0,R0,R2
\ 0000000A 0860 STR R0,[R1, #+0]
353 }
\ 0000000C 7047 BX LR ;; return
354
355 /*******************************************************************************
356 * Function Name : RCC_GetSYSCLKSource
357 * Description : Returns the clock source used as system clock.
358 * Input : None
359 * Output : None
360 * Return : The clock source used as system clock. The returned value can
361 * be one of the following:
362 * - 0x00: HSI used as system clock
363 * - 0x04: HSE used as system clock
364 * - 0x08: PLL used as system clock
365 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
366 u8 RCC_GetSYSCLKSource(void)
367 {
368 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
\ RCC_GetSYSCLKSource:
\ 00000000 .... LDR.N R0,??DataTable14 ;; 0x40021004
\ 00000002 0068 LDR R0,[R0, #+0]
\ 00000004 10F00C00 ANDS R0,R0,#0xC
\ 00000008 7047 BX LR ;; return
369 }
370
371 /*******************************************************************************
372 * Function Name : RCC_HCLKConfig
373 * Description : Configures the AHB clock (HCLK).
374 * Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is
375 * derived from the system clock (SYSCLK).
376 * This parameter can be one of the following values:
377 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
378 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
379 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
380 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
381 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
382 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
383 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
384 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
385 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
386 * Output : None
387 * Return : None
388 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
389 void RCC_HCLKConfig(u32 RCC_SYSCLK)
390 {
391 u32 tmpreg = 0;
392
393 /* Check the parameters */
394 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
395
396 tmpreg = RCC->CFGR;
\ RCC_HCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
397
398 /* Clear HPRE[3:0] bits */
399 tmpreg &= CFGR_HPRE_Reset_Mask;
400
401 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
402 tmpreg |= RCC_SYSCLK;
403
404 /* Store the new value */
405 RCC->CFGR = tmpreg;
\ 00000004 F023 MOVS R3,#+240
\ 00000006 9A43 BICS R2,R2,R3
\ 00000008 1043 ORRS R0,R0,R2
\ 0000000A 0860 STR R0,[R1, #+0]
406 }
\ 0000000C 7047 BX LR ;; return
407
408 /*******************************************************************************
409 * Function Name : RCC_PCLK1Config
410 * Description : Configures the Low Speed APB clock (PCLK1).
411 * Input : - RCC_HCLK: defines the APB1 clock divider. This clock is
412 * derived from the AHB clock (HCLK).
413 * This parameter can be one of the following values:
414 * - RCC_HCLK_Div1: APB1 clock = HCLK
415 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
416 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
417 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
418 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
419 * Output : None
420 * Return : None
421 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
422 void RCC_PCLK1Config(u32 RCC_HCLK)
423 {
424 u32 tmpreg = 0;
425
426 /* Check the parameters */
427 assert_param(IS_RCC_PCLK(RCC_HCLK));
428
429 tmpreg = RCC->CFGR;
\ RCC_PCLK1Config:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
430
431 /* Clear PPRE1[2:0] bits */
432 tmpreg &= CFGR_PPRE1_Reset_Mask;
433
434 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
435 tmpreg |= RCC_HCLK;
436
437 /* Store the new value */
438 RCC->CFGR = tmpreg;
\ 00000004 7FF4E063 MVNS R3,#+1792
\ 00000008 1340 ANDS R3,R3,R2
\ 0000000A 1843 ORRS R0,R0,R3
\ 0000000C 0860 STR R0,[R1, #+0]
439 }
\ 0000000E 7047 BX LR ;; return
440
441 /*******************************************************************************
442 * Function Name : RCC_PCLK2Config
443 * Description : Configures the High Speed APB clock (PCLK2).
444 * Input : - RCC_HCLK: defines the APB2 clock divider. This clock is
445 * derived from the AHB clock (HCLK).
446 * This parameter can be one of the following values:
447 * - RCC_HCLK_Div1: APB2 clock = HCLK
448 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
449 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
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