📄 stm32f10x_rcc.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 KICKSTART 26/Dec/2008 18:22:07 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Stack alignment = 4 #
# Source file = F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_r #
# cc.c #
# Command line = F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_r #
# cc.c -lCN F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3 #
# 210E-EVAL\IAR\OS-Probe\Flash\List\ -o #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\Obj\ -z6 --no_unroll --no_inline #
# --no_tbaa --no_scheduling --debug --cpu_mode thumb #
# --endian little --cpu cortex-M3 --stack_align 4 -e #
# --fpu None --dlib_config "E:\Program Files\IAR #
# Systems\Embedded Workbench 4.0 #
# Kickstart\arm\LIB\dl7mptnnl8n.h" -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ #
# ST\STM3210E-EVAL\IAR\OS-Probe\..\BSP\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\CPU\ST\STM32\inc\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-CPU\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-CPU\ARM-Cortex-M3\IAR #
# \ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E- #
# EVAL\IAR\OS-Probe\..\..\..\..\..\uC-LCD\Source\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-LIB\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uCOS-II\Ports\ARM-Cortex #
# -M3\Generic\IAR\ -I F:\PROJECT\STM32_UCOSII\EvalBoar #
# ds\ST\STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\..\uCOS #
# -II\Source\ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ST #
# \STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\..\uC-Probe\ #
# Target\Communication\Generic\RS-232\Source\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-Probe\Target\Communic #
# ation\Generic\RS-232\Ports\ST\STM32\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-Probe\Target\Communic #
# ation\Generic\Source\ -I F:\PROJECT\STM32_UCOSII\Eva #
# lBoards\ST\STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\.. #
# \uC-Probe\Target\Plugins\uCOS-II\ -I "E:\Program #
# Files\IAR Systems\Embedded Workbench 4.0 #
# Kickstart\arm\INC\" #
# List file = F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\List\stm32f10x_rcc.lst #
# Object file = F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\Obj\stm32f10x_rcc.r79 #
# #
# #
##############################################################################
F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_rcc.c
1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2 * File Name : stm32f10x_rcc.c
3 * Author : MCD Application Team
4 * Version : V2.0
5 * Date : 05/23/2008
6 * Description : This file provides all the RCC firmware functions.
7 ********************************************************************************
8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
15 * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
16 *******************************************************************************/
17
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32f10x_rcc.h"
20
21 /* Private typedef -----------------------------------------------------------*/
22 /* Private define ------------------------------------------------------------*/
23 /* ------------ RCC registers bit address in the alias region ----------- */
24 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
25
26 /* --- CR Register ---*/
27 /* Alias word address of HSION bit */
28 #define CR_OFFSET (RCC_OFFSET + 0x00)
29 #define HSION_BitNumber 0x00
30 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
31
32 /* Alias word address of PLLON bit */
33 #define PLLON_BitNumber 0x18
34 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
35
36 /* Alias word address of CSSON bit */
37 #define CSSON_BitNumber 0x13
38 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
39
40 /* --- CFGR Register ---*/
41 /* Alias word address of USBPRE bit */
42 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
43 #define USBPRE_BitNumber 0x16
44 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
45
46 /* --- BDCR Register ---*/
47 /* Alias word address of RTCEN bit */
48 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
49 #define RTCEN_BitNumber 0x0F
50 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
51
52 /* Alias word address of BDRST bit */
53 #define BDRST_BitNumber 0x10
54 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
55
56 /* --- CSR Register ---*/
57 /* Alias word address of LSION bit */
58 #define CSR_OFFSET (RCC_OFFSET + 0x24)
59 #define LSION_BitNumber 0x00
60 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
61
62 /* ---------------------- RCC registers bit mask ------------------------ */
63 /* CR register bit mask */
64 #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
65 #define CR_HSEBYP_Set ((u32)0x00040000)
66 #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
67 #define CR_HSEON_Set ((u32)0x00010000)
68 #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
69
70 /* CFGR register bit mask */
71 #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
72 #define CFGR_PLLMull_Mask ((u32)0x003C0000)
73 #define CFGR_PLLSRC_Mask ((u32)0x00010000)
74 #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
75 #define CFGR_SWS_Mask ((u32)0x0000000C)
76 #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
77 #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
78 #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
79 #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
80 #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
81 #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
82 #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
83 #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
84 #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
85
86 /* CSR register bit mask */
87 #define CSR_RMVF_Set ((u32)0x01000000)
88
89 /* RCC Flag Mask */
90 #define FLAG_Mask ((u8)0x1F)
91
92 /* Typical Value of the HSI in Hz */
93 #define HSI_Value ((u32)8000000)
94
95 /* CIR register byte 2 (Bits[15:8]) base address */
96 #define CIR_BYTE2_ADDRESS ((u32)0x40021009)
97 /* CIR register byte 3 (Bits[23:16]) base address */
98 #define CIR_BYTE3_ADDRESS ((u32)0x4002100A)
99
100 /* CFGR register byte 4 (Bits[31:24]) base address */
101 #define CFGR_BYTE4_ADDRESS ((u32)0x40021007)
102
103 /* BDCR register base address */
104 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
105
106 /* Time out for HSE start up */
107 #define HSEStartUp_TimeOut ((u16)0x01FF)
108
109 /* Private macro -------------------------------------------------------------*/
110 /* Private variables ---------------------------------------------------------*/
\ In segment DATA_C, align 4, align-sorted
111 static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
\ APBAHBPrescTable:
\ 00000000 000000000102 DC8 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9
\ 030401020304
\ 06070809
\ 00000010 02040608 DC8 2, 4, 6, 8
112 static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
113
\ In segment DATA_Z, align 4, align-sorted
114 static volatile FlagStatus HSEStatus;
\ HSEStatus:
\ 00000000 DS8 1
\ 00000001 DS8 3
\ 00000004 DS8 4
115 static vu32 StartUpCounter = 0;
116
117 /* Private function prototypes -----------------------------------------------*/
118 /* Private functions ---------------------------------------------------------*/
119
120 /*******************************************************************************
121 * Function Name : RCC_DeInit
122 * Description : Resets the RCC clock configuration to the default reset state.
123 * Input : None
124 * Output : None
125 * Return : None
126 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
127 void RCC_DeInit(void)
128 {
129 /* Set HSION bit */
130 RCC->CR |= (u32)0x00000001;
\ RCC_DeInit:
\ 00000000 .... LDR.N R0,??DataTable15 ;; 0x40021000
\ 00000002 0168 LDR R1,[R0, #+0]
\ 00000004 51F00101 ORRS R1,R1,#0x1
\ 00000008 0160 STR R1,[R0, #+0]
131
132 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
133 RCC->CFGR &= (u32)0xF8FF0000;
\ 0000000A .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 0000000C 0A68 LDR R2,[R1, #+0]
\ 0000000E 0A4B LDR.N R3,??RCC_DeInit_0 ;; 0xfffffffff8ff0000
\ 00000010 1340 ANDS R3,R3,R2
\ 00000012 0B60 STR R3,[R1, #+0]
134
135 /* Reset HSEON, CSSON and PLLON bits */
136 RCC->CR &= (u32)0xFEF6FFFF;
\ 00000014 0268 LDR R2,[R0, #+0]
\ 00000016 094B LDR.N R3,??RCC_DeInit_0+0x4 ;; 0xfffffffffef6ffff
\ 00000018 1340 ANDS R3,R3,R2
\ 0000001A 0360 STR R3,[R0, #+0]
137
138 /* Reset HSEBYP bit */
139 RCC->CR &= (u32)0xFFFBFFFF;
\ 0000001C 0268 LDR R2,[R0, #+0]
\ 0000001E 7FF48023 MVNS R3,#+262144
\ 00000022 1340 ANDS R3,R3,R2
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