📄 stm32f10x_dma.lst
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565 * - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
566 * Output : None
567 * Return : The new state of DMA_IT (SET or RESET).
568 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
569 ITStatus DMA_GetITStatus(u32 DMA_IT)
570 {
571 ITStatus bitstatus = RESET;
572 u32 tmpreg = 0;
573
574 /* Check the parameters */
575 assert_param(IS_DMA_GET_IT(DMA_IT));
576
577 /* Calculate the used DMA */
578 if ((DMA_IT & FLAG_Mask) != (u32)RESET)
\ DMA_GetITStatus:
\ 00000000 C100 LSLS R1,R0,#+3
\ 00000002 02D5 BPL.N ??DMA_GetITStatus_0
579 {
580 /* Get DMA2 ISR register value */
581 tmpreg = DMA2->ISR ;
\ 00000004 .... LDR.N R1,??DataTable6 ;; 0x40020400
\ 00000006 0968 LDR R1,[R1, #+0]
\ 00000008 01E0 B.N ??DMA_GetITStatus_1
582 }
583 else
584 {
585 /* Get DMA1 ISR register value */
586 tmpreg = DMA1->ISR ;
\ ??DMA_GetITStatus_0:
\ 0000000A .... LDR.N R1,??DataTable7 ;; 0x40020000
\ 0000000C 0968 LDR R1,[R1, #+0]
587 }
588
589 /* Check the status of the specified DMA interrupt */
590 if ((tmpreg & DMA_IT) != (u32)RESET)
\ ??DMA_GetITStatus_1:
\ 0000000E 0840 ANDS R0,R0,R1
\ 00000010 01D0 BEQ.N ??DMA_GetITStatus_2
591 {
592 /* DMA_IT is set */
593 bitstatus = SET;
\ 00000012 0120 MOVS R0,#+1
\ 00000014 7047 BX LR
594 }
595 else
596 {
597 /* DMA_IT is reset */
598 bitstatus = RESET;
\ ??DMA_GetITStatus_2:
\ 00000016 0020 MOVS R0,#+0
599 }
600 /* Return the DMA_IT status */
601 return bitstatus;
\ 00000018 7047 BX LR ;; return
602 }
603
604 /*******************************************************************************
605 * Function Name : DMA_ClearITPendingBit
606 * Description : Clears the DMAy Channelx抯 interrupt pending bits.
607 * Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
608 * This parameter can be any combination (for the same DMA) of
609 * the following values:
610 * - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
611 * - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
612 * - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
613 * - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
614 * - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
615 * - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
616 * - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
617 * - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
618 * - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
619 * - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
620 * - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
621 * - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
622 * - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
623 * - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
624 * - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
625 * - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
626 * - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
627 * - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
628 * - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
629 * - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
630 * - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
631 * - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
632 * - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
633 * - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
634 * - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
635 * - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
636 * - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
637 * - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
638 * - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
639 * - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
640 * - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
641 * - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
642 * - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
643 * - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
644 * - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
645 * - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
646 * - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
647 * - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
648 * - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
649 * - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
650 * - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
651 * - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
652 * - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
653 * - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
654 * - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
655 * - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
656 * - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
657 * - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
658 * Output : None
659 * Return : None
660 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
661 void DMA_ClearITPendingBit(u32 DMA_IT)
662 {
663 /* Check the parameters */
664 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
665
666 /* Calculate the used DMA */
667 if ((DMA_IT & FLAG_Mask) != (u32)RESET)
\ DMA_ClearITPendingBit:
\ 00000000 C100 LSLS R1,R0,#+3
\ 00000002 02D5 BPL.N ??DMA_ClearITPendingBit_0
668 {
669 /* Clear the selected DMA interrupt pending bits */
670 DMA2->IFCR = DMA_IT;
\ 00000004 .... LDR.N R1,??DataTable8 ;; 0x40020404
\ 00000006 0860 STR R0,[R1, #+0]
\ 00000008 7047 BX LR
671 }
672 else
673 {
674 /* Clear the selected DMA interrupt pending bits */
675 DMA1->IFCR = DMA_IT;
\ ??DMA_ClearITPendingBit_0:
\ 0000000A .... LDR.N R1,??DataTable9 ;; 0x40020004
\ 0000000C 0860 STR R0,[R1, #+0]
676 }
677 }
\ 0000000E 7047 BX LR ;; return
\ In segment CODE, align 4, keep-with-next
\ ??DataTable6:
\ 00000000 00040240 DC32 0x40020400
\ In segment CODE, align 4, keep-with-next
\ ??DataTable7:
\ 00000000 00000240 DC32 0x40020000
\ In segment CODE, align 4, keep-with-next
\ ??DataTable8:
\ 00000000 04040240 DC32 0x40020404
\ In segment CODE, align 4, keep-with-next
\ ??DataTable9:
\ 00000000 04000240 DC32 0x40020004
678
679 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
680
Maximum stack usage in bytes:
Function CSTACK
-------- ------
DMA_ClearFlag 0
DMA_ClearITPendingBit 0
DMA_Cmd 0
DMA_DeInit 4
DMA_GetCurrDataCounter 0
DMA_GetFlagStatus 0
DMA_GetITStatus 0
DMA_ITConfig 0
DMA_Init 0
DMA_StructInit 0
Segment part sizes:
Function/Label Bytes
-------------- -----
DMA_DeInit 204
DMA_Init 60
DMA_StructInit 26
DMA_Cmd 22
DMA_ITConfig 18
DMA_GetCurrDataCounter 6
DMA_GetFlagStatus 26
DMA_ClearFlag 16
DMA_GetITStatus 26
DMA_ClearITPendingBit 16
??DataTable6 4
??DataTable7 4
??DataTable8 4
??DataTable9 4
436 bytes in segment CODE
436 bytes of CODE memory
Errors: none
Warnings: none
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