📄 stm32f10x_dma.lst
字号:
\ ??DMA_DeInit_3:
\ 00000064 0868 LDR R0,[R1, #+0]
\ 00000066 50F47060 ORRS R0,R0,#0xF00
\ 0000006A 0860 STR R0,[R1, #+0]
\ 0000006C 00BD POP {PC}
100 break;
101
102 case DMA1_Channel4_BASE:
103 /* Reset interrupt pending bits for DMA1 Channel4 */
104 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
\ ??DMA_DeInit_4:
\ 0000006E 0868 LDR R0,[R1, #+0]
\ 00000070 50F47040 ORRS R0,R0,#0xF000
\ 00000074 0860 STR R0,[R1, #+0]
\ 00000076 00BD POP {PC}
105 break;
106
107 case DMA1_Channel5_BASE:
108 /* Reset interrupt pending bits for DMA1 Channel5 */
109 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
\ ??DMA_DeInit_5:
\ 00000078 0868 LDR R0,[R1, #+0]
\ 0000007A 50F47020 ORRS R0,R0,#0xF0000
\ 0000007E 0860 STR R0,[R1, #+0]
\ 00000080 00BD POP {PC}
110 break;
111
112 case DMA1_Channel6_BASE:
113 /* Reset interrupt pending bits for DMA1 Channel6 */
114 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
\ ??DMA_DeInit_6:
\ 00000082 0868 LDR R0,[R1, #+0]
\ 00000084 50F47000 ORRS R0,R0,#0xF00000
\ 00000088 0860 STR R0,[R1, #+0]
\ 0000008A 00BD POP {PC}
115 break;
116
117 case DMA1_Channel7_BASE:
118 /* Reset interrupt pending bits for DMA1 Channel7 */
119 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
\ ??DMA_DeInit_7:
\ 0000008C 0868 LDR R0,[R1, #+0]
\ 0000008E 50F07060 ORRS R0,R0,#0xF000000
\ 00000092 0860 STR R0,[R1, #+0]
\ 00000094 00BD POP {PC}
120 break;
121
122 case DMA2_Channel1_BASE:
123 /* Reset interrupt pending bits for DMA2 Channel1 */
124 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
\ ??DMA_DeInit_8:
\ 00000096 1068 LDR R0,[R2, #+0]
\ 00000098 50F00F00 ORRS R0,R0,#0xF
\ 0000009C 1060 STR R0,[R2, #+0]
\ 0000009E 00BD POP {PC}
125 break;
126
127 case DMA2_Channel2_BASE:
128 /* Reset interrupt pending bits for DMA2 Channel2 */
129 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
\ ??DMA_DeInit_9:
\ 000000A0 1068 LDR R0,[R2, #+0]
\ 000000A2 50F0F000 ORRS R0,R0,#0xF0
\ 000000A6 1060 STR R0,[R2, #+0]
\ 000000A8 00BD POP {PC}
130 break;
131
132 case DMA2_Channel3_BASE:
133 /* Reset interrupt pending bits for DMA2 Channel3 */
134 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
\ ??DMA_DeInit_10:
\ 000000AA 1068 LDR R0,[R2, #+0]
\ 000000AC 50F47060 ORRS R0,R0,#0xF00
\ 000000B0 1060 STR R0,[R2, #+0]
\ 000000B2 00BD POP {PC}
135 break;
136
137 case DMA2_Channel4_BASE:
138 /* Reset interrupt pending bits for DMA2 Channel4 */
139 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
\ ??DMA_DeInit_11:
\ 000000B4 1068 LDR R0,[R2, #+0]
\ 000000B6 50F47040 ORRS R0,R0,#0xF000
\ 000000BA 1060 STR R0,[R2, #+0]
\ 000000BC 00BD POP {PC}
140 break;
141
142 case DMA2_Channel5_BASE:
143 /* Reset interrupt pending bits for DMA2 Channel5 */
144 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
\ ??DMA_DeInit_12:
\ 000000BE 1068 LDR R0,[R2, #+0]
\ 000000C0 50F47020 ORRS R0,R0,#0xF0000
\ 000000C4 1060 STR R0,[R2, #+0]
145 break;
146
147 default:
148 break;
149 }
150 }
\ 000000C6 00BD POP {PC} ;; return
\ ??DMA_DeInit_0:
\ 000000C8 08000240 DC32 0x40020008
151
152 /*******************************************************************************
153 * Function Name : DMA_Init
154 * Description : Initializes the DMAy Channelx according to the specified
155 * parameters in the DMA_InitStruct.
156 * Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
157 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
158 * DMA Channel.
159 * - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
160 * contains the configuration information for the specified
161 * DMA Channel.
162 * Output : None
163 * Return : None
164 ******************************************************************************/
\ In segment CODE, align 4, keep-with-next
165 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
166 {
167 u32 tmpreg = 0;
168
169 /* Check the parameters */
170 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
171 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
172 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
173 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
174 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
175 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
176 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
177 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
178 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
179 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
180
181 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
182 /* Get the DMAy_Channelx CCR value */
183 tmpreg = DMAy_Channelx->CCR;
\ DMA_Init:
\ 00000000 0268 LDR R2,[R0, #+0]
184 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
185 tmpreg &= CCR_CLEAR_Mask;
186 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
187 /* Set DIR bit according to DMA_DIR value */
188 /* Set CIRC bit according to DMA_Mode value */
189 /* Set PINC bit according to DMA_PeripheralInc value */
190 /* Set MINC bit according to DMA_MemoryInc value */
191 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
192 /* Set MSIZE bits according to DMA_MemoryDataSize value */
193 /* Set PL bits according to DMA_Priority value */
194 /* Set the MEM2MEM bit according to DMA_M2M value */
195 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
196 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
197 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
198 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
199 /* Write to DMAy Channelx CCR */
200 DMAy_Channelx->CCR = tmpreg;
\ 00000002 0D4B LDR.N R3,??DMA_Init_0 ;; 0xffffffffffff800f
\ 00000004 1340 ANDS R3,R3,R2
\ 00000006 8A68 LDR R2,[R1, #+8]
\ 00000008 1A43 ORRS R2,R2,R3
\ 0000000A 0B6A LDR R3,[R1, #+32]
\ 0000000C 1343 ORRS R3,R3,R2
\ 0000000E 0A69 LDR R2,[R1, #+16]
\ 00000010 1A43 ORRS R2,R2,R3
\ 00000012 4B69 LDR R3,[R1, #+20]
\ 00000014 1343 ORRS R3,R3,R2
\ 00000016 8A69 LDR R2,[R1, #+24]
\ 00000018 1A43 ORRS R2,R2,R3
\ 0000001A CB69 LDR R3,[R1, #+28]
\ 0000001C 1343 ORRS R3,R3,R2
\ 0000001E 4A6A LDR R2,[R1, #+36]
\ 00000020 1A43 ORRS R2,R2,R3
\ 00000022 8B6A LDR R3,[R1, #+40]
\ 00000024 1343 ORRS R3,R3,R2
\ 00000026 0360 STR R3,[R0, #+0]
201
202 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
203 /* Write to DMAy Channelx CNDTR */
204 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
\ 00000028 CA68 LDR R2,[R1, #+12]
\ 0000002A 4260 STR R2,[R0, #+4]
205
206 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
207 /* Write to DMAy Channelx CPAR */
208 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
\ 0000002C 0A68 LDR R2,[R1, #+0]
\ 0000002E 8260 STR R2,[R0, #+8]
209
210 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
211 /* Write to DMAy Channelx CMAR */
212 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
\ 00000030 4968 LDR R1,[R1, #+4]
\ 00000032 C160 STR R1,[R0, #+12]
213 }
\ 00000034 7047 BX LR ;; return
\ 00000036 00BF Nop
\ ??DMA_Init_0:
\ 00000038 0F80FFFF DC32 0xffffffffffff800f
214
215 /*******************************************************************************
216 * Function Name : DMA_StructInit
217 * Description : Fills each DMA_InitStruct member with its default value.
218 * Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
219 * which will be initialized.
220 * Output : None
221 * Return : None
222 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
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