📄 stm32f10x_dma.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 KICKSTART 26/Dec/2008 18:22:05 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = thumb #
# Endian = little #
# Stack alignment = 4 #
# Source file = F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_d #
# ma.c #
# Command line = F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_d #
# ma.c -lCN F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3 #
# 210E-EVAL\IAR\OS-Probe\Flash\List\ -o #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\Obj\ -z6 --no_unroll --no_inline #
# --no_tbaa --no_scheduling --debug --cpu_mode thumb #
# --endian little --cpu cortex-M3 --stack_align 4 -e #
# --fpu None --dlib_config "E:\Program Files\IAR #
# Systems\Embedded Workbench 4.0 #
# Kickstart\arm\LIB\dl7mptnnl8n.h" -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ #
# ST\STM3210E-EVAL\IAR\OS-Probe\..\BSP\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\CPU\ST\STM32\inc\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-CPU\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-CPU\ARM-Cortex-M3\IAR #
# \ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E- #
# EVAL\IAR\OS-Probe\..\..\..\..\..\uC-LCD\Source\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-LIB\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uCOS-II\Ports\ARM-Cortex #
# -M3\Generic\IAR\ -I F:\PROJECT\STM32_UCOSII\EvalBoar #
# ds\ST\STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\..\uCOS #
# -II\Source\ -I F:\PROJECT\STM32_UCOSII\EvalBoards\ST #
# \STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\..\uC-Probe\ #
# Target\Communication\Generic\RS-232\Source\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-Probe\Target\Communic #
# ation\Generic\RS-232\Ports\ST\STM32\ -I #
# F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\..\..\..\..\..\uC-Probe\Target\Communic #
# ation\Generic\Source\ -I F:\PROJECT\STM32_UCOSII\Eva #
# lBoards\ST\STM3210E-EVAL\IAR\OS-Probe\..\..\..\..\.. #
# \uC-Probe\Target\Plugins\uCOS-II\ -I "E:\Program #
# Files\IAR Systems\Embedded Workbench 4.0 #
# Kickstart\arm\INC\" #
# List file = F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\List\stm32f10x_dma.lst #
# Object file = F:\PROJECT\STM32_UCOSII\EvalBoards\ST\STM3210E-EVAL\ #
# IAR\OS-Probe\Flash\Obj\stm32f10x_dma.r79 #
# #
# #
##############################################################################
F:\PROJECT\STM32_UCOSII\CPU\ST\STM32\src\stm32f10x_dma.c
1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2 * File Name : stm32f10x_dma.c
3 * Author : MCD Application Team
4 * Version : V2.0
5 * Date : 05/23/2008
6 * Description : This file provides all the DMA firmware functions.
7 ********************************************************************************
8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
15 * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
16 *******************************************************************************/
17
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32f10x_dma.h"
20 #include "stm32f10x_rcc.h"
21
22 /* Private typedef -----------------------------------------------------------*/
23 /* Private define ------------------------------------------------------------*/
24 /* DMA ENABLE mask */
25 #define CCR_ENABLE_Set ((u32)0x00000001)
26 #define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
27
28 /* DMA1 Channelx interrupt pending bit masks */
29 #define DMA1_Channel1_IT_Mask ((u32)0x0000000F)
30 #define DMA1_Channel2_IT_Mask ((u32)0x000000F0)
31 #define DMA1_Channel3_IT_Mask ((u32)0x00000F00)
32 #define DMA1_Channel4_IT_Mask ((u32)0x0000F000)
33 #define DMA1_Channel5_IT_Mask ((u32)0x000F0000)
34 #define DMA1_Channel6_IT_Mask ((u32)0x00F00000)
35 #define DMA1_Channel7_IT_Mask ((u32)0x0F000000)
36
37 /* DMA2 Channelx interrupt pending bit masks */
38 #define DMA2_Channel1_IT_Mask ((u32)0x0000000F)
39 #define DMA2_Channel2_IT_Mask ((u32)0x000000F0)
40 #define DMA2_Channel3_IT_Mask ((u32)0x00000F00)
41 #define DMA2_Channel4_IT_Mask ((u32)0x0000F000)
42 #define DMA2_Channel5_IT_Mask ((u32)0x000F0000)
43
44 /* DMA2 FLAG mask */
45 #define FLAG_Mask ((u32)0x10000000)
46
47 /* DMA registers Masks */
48 #define CCR_CLEAR_Mask ((u32)0xFFFF800F)
49
50 /* Private macro -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52 /* Private function prototypes -----------------------------------------------*/
53 /* Private functions ---------------------------------------------------------*/
54
55 /*******************************************************************************
56 * Function Name : DMA_DeInit
57 * Description : Deinitializes the DMAy Channelx registers to their default reset
58 * values.
59 * Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
60 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
61 * DMA Channel.
62 * Output : None
63 * Return : None
64 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
65 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
66 {
\ DMA_DeInit:
\ 00000000 00B5 PUSH {LR}
67 /* Check the parameters */
68 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
69
70 /* Disable the selected DMAy Channelx */
71 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
\ 00000002 0168 LDR R1,[R0, #+0]
\ 00000004 0122 MOVS R2,#+1
\ 00000006 9143 BICS R1,R1,R2
\ 00000008 0160 STR R1,[R0, #+0]
72
73 /* Reset DMAy Channelx control register */
74 DMAy_Channelx->CCR = 0;
\ 0000000A 0021 MOVS R1,#+0
\ 0000000C 0160 STR R1,[R0, #+0]
75
76 /* Reset DMAy Channelx remaining bytes register */
77 DMAy_Channelx->CNDTR = 0;
\ 0000000E 4160 STR R1,[R0, #+4]
78
79 /* Reset DMAy Channelx peripheral address register */
80 DMAy_Channelx->CPAR = 0;
\ 00000010 8160 STR R1,[R0, #+8]
81
82 /* Reset DMAy Channelx memory address register */
83 DMAy_Channelx->CMAR = 0;
\ 00000012 C160 STR R1,[R0, #+12]
84
85 switch (*(u32*)&DMAy_Channelx)
\ 00000014 .... LDR.N R1,??DataTable9 ;; 0x40020004
\ 00000016 .... LDR.N R2,??DataTable8 ;; 0x40020404
\ 00000018 2B4B LDR.N R3,??DMA_DeInit_0 ;; 0x40020008
\ 0000001A C01A SUBS R0,R0,R3
\ 0000001C 18D0 BEQ.N ??DMA_DeInit_1
\ 0000001E 1438 SUBS R0,R0,#+20
\ 00000020 1BD0 BEQ.N ??DMA_DeInit_2
\ 00000022 1438 SUBS R0,R0,#+20
\ 00000024 1ED0 BEQ.N ??DMA_DeInit_3
\ 00000026 1438 SUBS R0,R0,#+20
\ 00000028 21D0 BEQ.N ??DMA_DeInit_4
\ 0000002A 1438 SUBS R0,R0,#+20
\ 0000002C 24D0 BEQ.N ??DMA_DeInit_5
\ 0000002E 1438 SUBS R0,R0,#+20
\ 00000030 27D0 BEQ.N ??DMA_DeInit_6
\ 00000032 1438 SUBS R0,R0,#+20
\ 00000034 2AD0 BEQ.N ??DMA_DeInit_7
\ 00000036 5FF46273 MOVS R3,#+904
\ 0000003A C01A SUBS R0,R0,R3
\ 0000003C 2BD0 BEQ.N ??DMA_DeInit_8
\ 0000003E 1438 SUBS R0,R0,#+20
\ 00000040 2ED0 BEQ.N ??DMA_DeInit_9
\ 00000042 1438 SUBS R0,R0,#+20
\ 00000044 31D0 BEQ.N ??DMA_DeInit_10
\ 00000046 1438 SUBS R0,R0,#+20
\ 00000048 34D0 BEQ.N ??DMA_DeInit_11
\ 0000004A 1438 SUBS R0,R0,#+20
\ 0000004C 37D0 BEQ.N ??DMA_DeInit_12
\ 0000004E 00BD POP {PC}
86 {
87 case DMA1_Channel1_BASE:
88 /* Reset interrupt pending bits for DMA1 Channel1 */
89 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
\ ??DMA_DeInit_1:
\ 00000050 0868 LDR R0,[R1, #+0]
\ 00000052 50F00F00 ORRS R0,R0,#0xF
\ 00000056 0860 STR R0,[R1, #+0]
\ 00000058 00BD POP {PC}
90 break;
91
92 case DMA1_Channel2_BASE:
93 /* Reset interrupt pending bits for DMA1 Channel2 */
94 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
\ ??DMA_DeInit_2:
\ 0000005A 0868 LDR R0,[R1, #+0]
\ 0000005C 50F0F000 ORRS R0,R0,#0xF0
\ 00000060 0860 STR R0,[R1, #+0]
\ 00000062 00BD POP {PC}
95 break;
96
97 case DMA1_Channel3_BASE:
98 /* Reset interrupt pending bits for DMA1 Channel3 */
99 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
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