📄 stm32f10x_tim.lst
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\ 00000052 C989 LDRH R1,[R1, #+14]
\ 00000054 1143 ORRS R1,R1,R2
\ 00000056 55EA8102 ORRS R2,R5,R1, LSL #+2
398 }
399
400 /* Write to TIMx CR2 */
401 TIMx->CR2 = tmpcr2;
\ ??TIM_OC2Init_1:
\ 0000005A 8280 STRH R2,[R0, #+4]
402
403 /* Write to TIMx CCMR1 */
404 TIMx->CCMR1 = tmpccmrx;
\ 0000005C 0483 STRH R4,[R0, #+24]
405
406 /* Write to TIMx CCER */
407 TIMx->CCER = tmpccer;
\ 0000005E 0384 STRH R3,[R0, #+32]
408 }
\ 00000060 70BD POP {R4-R6,PC} ;; return
\ 00000062 00BF Nop
\ ??TIM_OC2Init_2:
\ 00000064 BFFF0000 DC32 0xffbf
\ 00000068 FF730000 DC32 0x73ff
409
410 /*******************************************************************************
411 * Function Name : TIM_OC3Init
412 * Description : Initializes the TIMx Channel3 according to the specified
413 * parameters in the TIM_OCInitStruct.
414 * Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
415 * peripheral.
416 * - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
417 * that contains the configuration information for the specified
418 * TIM peripheral.
419 * Output : None
420 * Return : None
421 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
422 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
423 {
\ TIM_OC3Init:
\ 00000000 70B5 PUSH {R4-R6,LR}
424 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
425
426 /* Check the parameters */
427 assert_param(IS_TIM_123458_PERIPH(TIMx));
428 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
429 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
430 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
431
432 /* Disable the Channel 2: Reset the CC2E Bit */
433 TIMx->CCER &= CCER_CC3E_Reset;
\ 00000002 028C LDRH R2,[R0, #+32]
\ 00000004 .... LDR.N R3,??DataTable17 ;; 0xfeff
\ 00000006 1340 ANDS R3,R3,R2
\ 00000008 0384 STRH R3,[R0, #+32]
434
435 /* Get the TIMx CCER register value */
436 tmpccer = TIMx->CCER;
\ 0000000A 048C LDRH R4,[R0, #+32]
437
438 /* Get the TIMx CR2 register value */
439 tmpcr2 = TIMx->CR2;
\ 0000000C 8288 LDRH R2,[R0, #+4]
440
441 /* Get the TIMx CCMR2 register value */
442 tmpccmrx = TIMx->CCMR2;
\ 0000000E 838B LDRH R3,[R0, #+28]
443
444 /* Reset the Output Compare Mode Bits */
445 tmpccmrx &= CCMR_OC13M_Mask;
446
447 /* Select the Output Compare Mode */
448 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\ 00000010 .... LDR.N R5,??DataTable18 ;; 0xff8f
\ 00000012 1D40 ANDS R5,R5,R3
\ 00000014 0B88 LDRH R3,[R1, #+0]
\ 00000016 2B43 ORRS R3,R3,R5
449
450 /* Reset the Output Polarity level */
451 tmpccer &= CCER_CC3P_Reset;
452
453 /* Set the Output Compare Polarity */
454 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8);
455
456 /* Set the Output State */
457 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8);
\ 00000018 .... LDR.N R5,??DataTable19 ;; 0xfdff
\ 0000001A 2540 ANDS R5,R5,R4
\ 0000001C 0C89 LDRH R4,[R1, #+8]
\ 0000001E 4E88 LDRH R6,[R1, #+2]
\ 00000020 2643 ORRS R6,R6,R4
\ 00000022 55EA0624 ORRS R4,R5,R6, LSL #+8
458
459 /* Set the Capture Compare Register value */
460 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
\ 00000026 CD88 LDRH R5,[R1, #+6]
\ 00000028 8587 STRH R5,[R0, #+60]
461
462 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
\ 0000002A .... LDR.N R5,??DataTable27 ;; 0x40012c00
\ 0000002C A842 CMP R0,R5
\ 0000002E 02D0 BEQ.N ??TIM_OC3Init_0
\ 00000030 .... LDR.N R5,??DataTable28 ;; 0x40013400
\ 00000032 A842 CMP R0,R5
\ 00000034 10D1 BNE.N ??TIM_OC3Init_1
463 {
464 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
465 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
466 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
467 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
468
469 /* Reset the Output N Polarity level */
470 tmpccer &= CCER_CC3NP_Reset;
471
472 /* Set the Output N Polarity */
473 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
474
475 /* Reset the Output N State */
476 tmpccer &= CCER_CC3NE_Reset;
477
478 /* Set the Output N State */
479 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8);
\ ??TIM_OC3Init_0:
\ 00000036 .... LDR.N R5,??DataTable22 ;; 0xf7ff
\ 00000038 2540 ANDS R5,R5,R4
\ 0000003A 4C89 LDRH R4,[R1, #+10]
\ 0000003C 55EA0424 ORRS R4,R5,R4, LSL #+8
\ 00000040 .... LDR.N R5,??DataTable23 ;; 0xfbff
\ 00000042 2540 ANDS R5,R5,R4
\ 00000044 8C88 LDRH R4,[R1, #+4]
\ 00000046 55EA0424 ORRS R4,R5,R4, LSL #+8
480
481 /* Reset the Ouput Compare and Output Compare N IDLE State */
482 tmpcr2 &= CR2_OIS3_Reset;
483 tmpcr2 &= CR2_OIS3N_Reset;
484
485 /* Set the Output Idle state */
486 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4);
487
488 /* Set the Output N Idle state */
489 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
\ 0000004A 054D LDR.N R5,??TIM_OC3Init_2 ;; 0x4fff
\ 0000004C 1540 ANDS R5,R5,R2
\ 0000004E 8A89 LDRH R2,[R1, #+12]
\ 00000050 C989 LDRH R1,[R1, #+14]
\ 00000052 1143 ORRS R1,R1,R2
\ 00000054 55EA0112 ORRS R2,R5,R1, LSL #+4
490 }
491
492 /* Write to TIMx CR2 */
493 TIMx->CR2 = tmpcr2;
\ ??TIM_OC3Init_1:
\ 00000058 8280 STRH R2,[R0, #+4]
494
495 /* Write to TIMx CCMR2 */
496 TIMx->CCMR2 = tmpccmrx;
\ 0000005A 8383 STRH R3,[R0, #+28]
497
498 /* Write to TIMx CCER */
499 TIMx->CCER = tmpccer;
\ 0000005C 0484 STRH R4,[R0, #+32]
500 }
\ 0000005E 70BD POP {R4-R6,PC} ;; return
\ ??TIM_OC3Init_2:
\ 00000060 FF4F0000 DC32 0x4fff
501
502 /*******************************************************************************
503 * Function Name : TIM_OC4Init
504 * Description : Initializes the TIMx Channel4 according to the specified
505 * parameters in the TIM_OCInitStruct.
506 * Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
507 * peripheral.
508 * - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
509 * that contains the configuration information for the specified
510 * TIM peripheral.
511 * Output : None
512 * Return : None
513 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
514 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
515 {
\ TIM_OC4Init:
\ 00000000 70B5 PUSH {R4-R6,LR}
516 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
517
518 /* Check the parameters */
519 assert_param(IS_TIM_123458_PERIPH(TIMx));
520 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
521 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
522 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
523
524 /* Disable the Channel 2: Reset the CC4E Bit */
525 TIMx->CCER &= CCER_CC4E_Reset;
\ 00000002 028C LDRH R2,[R0, #+32]
\ 00000004 .... LDR.N R3,??DataTable24 ;; 0xefff
\ 00000006 1340 ANDS R3,R3,R2
\ 00000008 0384 STRH R3,[R0, #+32]
526
527 /* Get the TIMx CCER register value */
528 tmpccer = TIMx->CCER;
\ 0000000A 038C LDRH R3,[R0, #+32]
529
530 /* Get the TIMx CR2 register value */
531 tmpcr2 = TIMx->CR2;
\ 0000000C 8288 LDRH R2,[R0, #+4]
532
533 /* Get the TIMx CCMR2 register value */
534 tmpccmrx = TIMx->CCMR2;
\ 0000000E 848B LDRH R4,[R0, #+28]
535
536 /* Reset the Output Compare Mode Bits */
537 tmpccmrx &= CCMR_OC24M_Mask;
538
539 /* Select the Output Compare Mode */
540 tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
\ 00000010 .... LDR.N R5,??DataTable25 ;; 0x8fff
\ 00000012 2540 ANDS R5,R5,R4
\ 00000014 0C88 LDRH R4,[R1, #+0]
\ 00000016 55EA0424 ORRS R4,R5,R4, LSL #+8
541
542 /* Reset the Output Polarity level */
543 tmpccer &= CCER_CC4P_Reset;
544
545 /* Set the Output Compare Polarity */
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