📄 stm32f10x_tim.lst
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255 /* Get the TIMx CR2 register value */
256 tmpcr2 = TIMx->CR2;
\ 0000000C 8288 LDRH R2,[R0, #+4]
257
258 /* Get the TIMx CCMR1 register value */
259 tmpccmrx = TIMx->CCMR1;
\ 0000000E 038B LDRH R3,[R0, #+24]
260
261 /* Reset the Output Compare Mode Bits */
262 tmpccmrx &= CCMR_OC13M_Mask;
263
264 /* Select the Output Compare Mode */
265 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\ 00000010 .... LDR.N R5,??DataTable18 ;; 0xff8f
\ 00000012 1D40 ANDS R5,R5,R3
\ 00000014 0B88 LDRH R3,[R1, #+0]
\ 00000016 2B43 ORRS R3,R3,R5
266
267 /* Reset the Output Polarity level */
268 tmpccer &= CCER_CC1P_Reset;
269
270 /* Set the Output Compare Polarity */
271 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
272
273 /* Set the Output State */
274 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
\ 00000018 .... LDR.N R5,??DataTable6 ;; 0xfffd
\ 0000001A 2540 ANDS R5,R5,R4
\ 0000001C 0E89 LDRH R6,[R1, #+8]
\ 0000001E 2E43 ORRS R6,R6,R5
\ 00000020 4C88 LDRH R4,[R1, #+2]
\ 00000022 3443 ORRS R4,R4,R6
275
276 /* Set the Capture Compare Register value */
277 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
\ 00000024 CD88 LDRH R5,[R1, #+6]
\ 00000026 8586 STRH R5,[R0, #+52]
278
279 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
\ 00000028 .... LDR.N R5,??DataTable27 ;; 0x40012c00
\ 0000002A A842 CMP R0,R5
\ 0000002C 02D0 BEQ.N ??TIM_OC1Init_0
\ 0000002E .... LDR.N R5,??DataTable28 ;; 0x40013400
\ 00000030 A842 CMP R0,R5
\ 00000032 0DD1 BNE.N ??TIM_OC1Init_1
280 {
281 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
282 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
283 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
284 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
285
286 /* Reset the Output N Polarity level */
287 tmpccer &= CCER_CC1NP_Reset;
288
289 /* Set the Output N Polarity */
290 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
291
292 /* Reset the Output N State */
293 tmpccer &= CCER_CC1NE_Reset;
294
295 /* Set the Output N State */
296 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
\ ??TIM_OC1Init_0:
\ 00000034 .... LDR.N R5,??DataTable9 ;; 0xfff7
\ 00000036 2540 ANDS R5,R5,R4
\ 00000038 4C89 LDRH R4,[R1, #+10]
\ 0000003A 2C43 ORRS R4,R4,R5
\ 0000003C .... LDR.N R5,??DataTable10 ;; 0xfffb
\ 0000003E 2540 ANDS R5,R5,R4
\ 00000040 8C88 LDRH R4,[R1, #+4]
\ 00000042 2C43 ORRS R4,R4,R5
297
298 /* Reset the Ouput Compare and Output Compare N IDLE State */
299 tmpcr2 &= CR2_OIS1_Reset;
300 tmpcr2 &= CR2_OIS1N_Reset;
301
302 /* Set the Output Idle state */
303 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
304
305 /* Set the Output N Idle state */
306 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
\ 00000044 044D LDR.N R5,??TIM_OC1Init_2 ;; 0x7cff
\ 00000046 1540 ANDS R5,R5,R2
\ 00000048 8E89 LDRH R6,[R1, #+12]
\ 0000004A 2E43 ORRS R6,R6,R5
\ 0000004C CA89 LDRH R2,[R1, #+14]
\ 0000004E 3243 ORRS R2,R2,R6
307 }
308 /* Write to TIMx CR2 */
309 TIMx->CR2 = tmpcr2;
\ ??TIM_OC1Init_1:
\ 00000050 8280 STRH R2,[R0, #+4]
310
311 /* Write to TIMx CCMR1 */
312 TIMx->CCMR1 = tmpccmrx;
\ 00000052 0383 STRH R3,[R0, #+24]
313
314 /* Write to TIMx CCER */
315 TIMx->CCER = tmpccer;
\ 00000054 0484 STRH R4,[R0, #+32]
316 }
\ 00000056 70BD POP {R4-R6,PC} ;; return
\ ??TIM_OC1Init_2:
\ 00000058 FF7C0000 DC32 0x7cff
317
318 /*******************************************************************************
319 * Function Name : TIM_OC2Init
320 * Description : Initializes the TIMx Channel2 according to the specified
321 * parameters in the TIM_OCInitStruct.
322 * Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
323 * peripheral.
324 * - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
325 * that contains the configuration information for the specified
326 * TIM peripheral.
327 * Output : None
328 * Return : None
329 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
330 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
331 {
\ TIM_OC2Init:
\ 00000000 70B5 PUSH {R4-R6,LR}
332 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
333
334 /* Check the parameters */
335 assert_param(IS_TIM_123458_PERIPH(TIMx));
336 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
337 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
338 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
339
340 /* Disable the Channel 2: Reset the CC2E Bit */
341 TIMx->CCER &= CCER_CC2E_Reset;
\ 00000002 028C LDRH R2,[R0, #+32]
\ 00000004 .... LDR.N R3,??DataTable11 ;; 0xffef
\ 00000006 1340 ANDS R3,R3,R2
\ 00000008 0384 STRH R3,[R0, #+32]
342
343 /* Get the TIMx CCER register value */
344 tmpccer = TIMx->CCER;
\ 0000000A 038C LDRH R3,[R0, #+32]
345
346 /* Get the TIMx CR2 register value */
347 tmpcr2 = TIMx->CR2;
\ 0000000C 8288 LDRH R2,[R0, #+4]
348
349 /* Get the TIMx CCMR1 register value */
350 tmpccmrx = TIMx->CCMR1;
\ 0000000E 048B LDRH R4,[R0, #+24]
351
352 /* Reset the Output Compare Mode Bits */
353 tmpccmrx &= CCMR_OC24M_Mask;
354
355 /* Select the Output Compare Mode */
356 tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
\ 00000010 .... LDR.N R5,??DataTable25 ;; 0x8fff
\ 00000012 2540 ANDS R5,R5,R4
\ 00000014 0C88 LDRH R4,[R1, #+0]
\ 00000016 55EA0424 ORRS R4,R5,R4, LSL #+8
357
358 /* Reset the Output Polarity level */
359 tmpccer &= CCER_CC2P_Reset;
360
361 /* Set the Output Compare Polarity */
362 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4);
363
364 /* Set the Output State */
365 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4);
\ 0000001A .... LDR.N R5,??DataTable13 ;; 0xffdf
\ 0000001C 1D40 ANDS R5,R5,R3
\ 0000001E 0B89 LDRH R3,[R1, #+8]
\ 00000020 4E88 LDRH R6,[R1, #+2]
\ 00000022 1E43 ORRS R6,R6,R3
\ 00000024 55EA0613 ORRS R3,R5,R6, LSL #+4
366
367 /* Set the Capture Compare Register value */
368 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
\ 00000028 CD88 LDRH R5,[R1, #+6]
\ 0000002A 0587 STRH R5,[R0, #+56]
369
370 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
\ 0000002C .... LDR.N R5,??DataTable27 ;; 0x40012c00
\ 0000002E A842 CMP R0,R5
\ 00000030 02D0 BEQ.N ??TIM_OC2Init_0
\ 00000032 .... LDR.N R5,??DataTable28 ;; 0x40013400
\ 00000034 A842 CMP R0,R5
\ 00000036 10D1 BNE.N ??TIM_OC2Init_1
371 {
372 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
373 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
374 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
375 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
376
377 /* Reset the Output N Polarity level */
378 tmpccer &= CCER_CC2NP_Reset;
379
380 /* Set the Output N Polarity */
381 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
382
383 /* Reset the Output N State */
384 tmpccer &= CCER_CC2NE_Reset;
385
386 /* Set the Output N State */
387 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4);
\ ??TIM_OC2Init_0:
\ 00000038 .... LDR.N R5,??DataTable16 ;; 0xff7f
\ 0000003A 1D40 ANDS R5,R5,R3
\ 0000003C 4B89 LDRH R3,[R1, #+10]
\ 0000003E 55EA0313 ORRS R3,R5,R3, LSL #+4
\ 00000042 084D LDR.N R5,??TIM_OC2Init_2 ;; 0xffbf
\ 00000044 1D40 ANDS R5,R5,R3
\ 00000046 8B88 LDRH R3,[R1, #+4]
\ 00000048 55EA0313 ORRS R3,R5,R3, LSL #+4
388
389 /* Reset the Ouput Compare and Output Compare N IDLE State */
390 tmpcr2 &= CR2_OIS2_Reset;
391 tmpcr2 &= CR2_OIS2N_Reset;
392
393 /* Set the Output Idle state */
394 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2);
395
396 /* Set the Output N Idle state */
397 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
\ 0000004C 064D LDR.N R5,??TIM_OC2Init_2+0x4 ;; 0x73ff
\ 0000004E 1540 ANDS R5,R5,R2
\ 00000050 8A89 LDRH R2,[R1, #+12]
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