📄 stm32f10x_tim.lst
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\ 00000030 8842 CMP R0,R1
\ 00000032 40D0 BEQ.N ??TIM_DeInit_8
\ 00000034 00BD POP {PC}
142 {
143 case TIM1_BASE:
144 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
\ ??TIM_DeInit_7:
\ 00000036 0121 MOVS R1,#+1
\ 00000038 C802 LSLS R0,R1,#+11
\ 0000003A ........ _BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
145 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
\ 0000003E 0021 MOVS R1,#+0
\ 00000040 5FF40060 MOVS R0,#+2048
\ 00000044 ........ _BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
\ 00000048 00BD POP {PC}
146 break;
147
148 case TIM2_BASE:
149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
\ ??TIM_DeInit_0:
\ 0000004A 0121 MOVS R1,#+1
\ 0000004C 0846 MOV R0,R1
\ 0000004E ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
\ 00000052 0021 MOVS R1,#+0
\ 00000054 0120 MOVS R0,#+1
\ 00000056 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 0000005A 00BD POP {PC}
151 break;
152
153 case TIM3_BASE:
154 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
\ ??TIM_DeInit_2:
\ 0000005C 0121 MOVS R1,#+1
\ 0000005E 0220 MOVS R0,#+2
\ 00000060 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
155 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
\ 00000064 0021 MOVS R1,#+0
\ 00000066 0220 MOVS R0,#+2
\ 00000068 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 0000006C 00BD POP {PC}
156 break;
157
158 case TIM4_BASE:
159 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
\ ??TIM_DeInit_3:
\ 0000006E 0121 MOVS R1,#+1
\ 00000070 0420 MOVS R0,#+4
\ 00000072 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
160 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
\ 00000076 0021 MOVS R1,#+0
\ 00000078 0420 MOVS R0,#+4
\ 0000007A ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 0000007E 00BD POP {PC}
161 break;
162
163 case TIM5_BASE:
164 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
\ ??TIM_DeInit_4:
\ 00000080 0121 MOVS R1,#+1
\ 00000082 0820 MOVS R0,#+8
\ 00000084 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
165 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
\ 00000088 0021 MOVS R1,#+0
\ 0000008A 0820 MOVS R0,#+8
\ 0000008C ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 00000090 00BD POP {PC}
166 break;
167
168 case TIM6_BASE:
169 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
\ ??TIM_DeInit_5:
\ 00000092 0121 MOVS R1,#+1
\ 00000094 1020 MOVS R0,#+16
\ 00000096 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
170 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
\ 0000009A 0021 MOVS R1,#+0
\ 0000009C 1020 MOVS R0,#+16
\ 0000009E ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 000000A2 00BD POP {PC}
171 break;
172
173 case TIM7_BASE:
174 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
\ ??TIM_DeInit_6:
\ 000000A4 0121 MOVS R1,#+1
\ 000000A6 2020 MOVS R0,#+32
\ 000000A8 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
175 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
\ 000000AC 0021 MOVS R1,#+0
\ 000000AE 2020 MOVS R0,#+32
\ 000000B0 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 000000B4 00BD POP {PC}
176 break;
177
178 case TIM8_BASE:
179 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
\ ??TIM_DeInit_8:
\ 000000B6 0121 MOVS R1,#+1
\ 000000B8 4803 LSLS R0,R1,#+13
\ 000000BA ........ _BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
180 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
\ 000000BE 0021 MOVS R1,#+0
\ 000000C0 5FF40050 MOVS R0,#+8192
\ 000000C4 ........ _BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
181 break;
182
183 default:
184 break;
185 }
186 }
\ 000000C8 00BD POP {PC} ;; return
\ 000000CA 00BF Nop
\ ??TIM_DeInit_1:
\ 000000CC 00040040 DC32 0x40000400
\ 000000D0 00080040 DC32 0x40000800
\ 000000D4 000C0040 DC32 0x40000c00
\ 000000D8 00100040 DC32 0x40001000
\ 000000DC 00140040 DC32 0x40001400
187
188 /*******************************************************************************
189 * Function Name : TIM_TimeBaseInit
190 * Description : Initializes the TIMx Time Base Unit peripheral according to
191 * the specified parameters in the TIM_TimeBaseInitStruct.
192 * Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
193 * peripheral.
194 * - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
195 * structure that contains the configuration information for
196 * the specified TIM peripheral.
197 * Output : None
198 * Return : None
199 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
200 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
201 {
\ TIM_TimeBaseInit:
\ 00000000 10B5 PUSH {R4,LR}
202 /* Check the parameters */
203 assert_param(IS_TIM_123458_PERIPH(TIMx));
204 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
205 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
206
207 /* Select the Counter Mode and set the clock division */
208 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
\ 00000002 0288 LDRH R2,[R0, #+0]
\ 00000004 12F08F02 ANDS R2,R2,#0x8F
\ 00000008 0280 STRH R2,[R0, #+0]
209 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
210 TIM_TimeBaseInitStruct->TIM_CounterMode;
\ 0000000A 0288 LDRH R2,[R0, #+0]
\ 0000000C CB88 LDRH R3,[R1, #+6]
\ 0000000E 4C88 LDRH R4,[R1, #+2]
\ 00000010 1C43 ORRS R4,R4,R3
\ 00000012 1443 ORRS R4,R4,R2
\ 00000014 0480 STRH R4,[R0, #+0]
211 /* Set the Autoreload value */
212 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
\ 00000016 8A88 LDRH R2,[R1, #+4]
\ 00000018 8285 STRH R2,[R0, #+44]
213
214 /* Set the Prescaler value */
215 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
\ 0000001A 0A88 LDRH R2,[R1, #+0]
\ 0000001C 0285 STRH R2,[R0, #+40]
216
217 /* Generate an update event to reload the Prescaler value immediatly */
218 TIMx->EGR = TIM_PSCReloadMode_Immediate;
\ 0000001E 0122 MOVS R2,#+1
\ 00000020 8282 STRH R2,[R0, #+20]
219
220 if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE))
\ 00000022 .... LDR.N R2,??DataTable27 ;; 0x40012c00
\ 00000024 9042 CMP R0,R2
\ 00000026 02D0 BEQ.N ??TIM_TimeBaseInit_0
\ 00000028 .... LDR.N R2,??DataTable28 ;; 0x40013400
\ 0000002A 9042 CMP R0,R2
\ 0000002C 01D1 BNE.N ??TIM_TimeBaseInit_1
221 {
222 /* Set the Repetition Counter value */
223 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
\ ??TIM_TimeBaseInit_0:
\ 0000002E 097A LDRB R1,[R1, #+8]
\ 00000030 0186 STRH R1,[R0, #+48]
224 }
225 }
\ ??TIM_TimeBaseInit_1:
\ 00000032 10BD POP {R4,PC} ;; return
226
227 /*******************************************************************************
228 * Function Name : TIM_OC1Init
229 * Description : Initializes the TIMx Channel1 according to the specified
230 * parameters in the TIM_OCInitStruct.
231 * Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
232 * peripheral.
233 * - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
234 * that contains the configuration information for the specified
235 * TIM peripheral.
236 * Output : None
237 * Return : None
238 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
239 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
240 {
\ TIM_OC1Init:
\ 00000000 70B5 PUSH {R4-R6,LR}
241 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
242
243 /* Check the parameters */
244 assert_param(IS_TIM_123458_PERIPH(TIMx));
245 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
246 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
247 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
248
249 /* Disable the Channel 1: Reset the CC1E Bit */
250 TIMx->CCER &= CCER_CC1E_Reset;
\ 00000002 028C LDRH R2,[R0, #+32]
\ 00000004 .... LDR.N R3,??DataTable4 ;; 0xfffe
\ 00000006 1340 ANDS R3,R3,R2
\ 00000008 0384 STRH R3,[R0, #+32]
251
252 /* Get the TIMx CCER register value */
253 tmpccer = TIMx->CCER;
\ 0000000A 048C LDRH R4,[R0, #+32]
254
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