📄 stm32f10x_spi.lst
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127 /* Get the SPIx CR1 value */
128 tmpreg = SPIx->CR1;
\ SPI_Init:
\ 00000000 0288 LDRH R2,[R0, #+0]
129 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
130 tmpreg &= CR1_CLEAR_Mask;
131 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
132 master/salve mode, CPOL and CPHA */
133 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
134 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
135 /* Set LSBFirst bit according to SPI_FirstBit value */
136 /* Set BR bits according to SPI_BaudRatePrescaler value */
137 /* Set CPOL bit according to SPI_CPOL value */
138 /* Set CPHA bit according to SPI_CPHA value */
139 tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
140 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
141 SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
142 SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
143 /* Write to SPIx CR1 */
144 SPIx->CR1 = tmpreg;
\ 00000002 12F44152 ANDS R2,R2,#0x3040
\ 00000006 0B88 LDRH R3,[R1, #+0]
\ 00000008 1343 ORRS R3,R3,R2
\ 0000000A 4A88 LDRH R2,[R1, #+2]
\ 0000000C 1A43 ORRS R2,R2,R3
\ 0000000E 8B88 LDRH R3,[R1, #+4]
\ 00000010 1343 ORRS R3,R3,R2
\ 00000012 CA88 LDRH R2,[R1, #+6]
\ 00000014 1A43 ORRS R2,R2,R3
\ 00000016 0B89 LDRH R3,[R1, #+8]
\ 00000018 1343 ORRS R3,R3,R2
\ 0000001A 4A89 LDRH R2,[R1, #+10]
\ 0000001C 1A43 ORRS R2,R2,R3
\ 0000001E 8B89 LDRH R3,[R1, #+12]
\ 00000020 1343 ORRS R3,R3,R2
\ 00000022 CA89 LDRH R2,[R1, #+14]
\ 00000024 1A43 ORRS R2,R2,R3
\ 00000026 0280 STRH R2,[R0, #+0]
145
146 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
147 SPIx->I2SCFGR &= SPI_Mode_Select;
\ 00000028 828B LDRH R2,[R0, #+28]
\ 0000002A .... LDR.N R3,??DataTable1 ;; 0xf7ff
\ 0000002C 1340 ANDS R3,R3,R2
\ 0000002E 8383 STRH R3,[R0, #+28]
148
149 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
150 /* Write to SPIx CRCPOLY */
151 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
\ 00000030 098A LDRH R1,[R1, #+16]
\ 00000032 0182 STRH R1,[R0, #+16]
152 }
\ 00000034 7047 BX LR ;; return
153
154 /*******************************************************************************
155 * Function Name : I2S_Init
156 * Description : Initializes the SPIx peripheral according to the specified
157 * parameters in the I2S_InitStruct.
158 * Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral
159 * (configured in I2S mode).
160 * - I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
161 * contains the configuration information for the specified
162 * SPI peripheral configured in I2S mode.
163 * Output : None
164 * Return : None
165 ******************************************************************************/
\ In segment CODE, align 4, keep-with-next
166 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
167 {
\ I2S_Init:
\ 00000000 2DE9F043 PUSH {R4-R9,LR}
\ 00000004 85B0 SUB SP,SP,#+20
\ 00000006 0400 MOVS R4,R0
\ 00000008 0D00 MOVS R5,R1
168 u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
169 u32 tmp = 0;
170 RCC_ClocksTypeDef RCC_Clocks;
171
172 /* Check the I2S parameters */
173 assert_param(IS_SPI_23_PERIPH(SPIx));
174 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
175 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
176 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
177 assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
178 assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
179 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
180
181 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
182
183 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
184 SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
\ 0000000A A08B LDRH R0,[R4, #+28]
\ 0000000C 2A49 LDR.N R1,??I2S_Init_0 ;; 0xf040
\ 0000000E 0140 ANDS R1,R1,R0
\ 00000010 A183 STRH R1,[R4, #+28]
185 SPIx->I2SPR = 0x0002;
\ 00000012 0220 MOVS R0,#+2
\ 00000014 8046 MOV R8,R0
\ 00000016 2084 STRH R0,[R4, #+32]
186
187 /* Get the I2SCFGR register value */
188 tmpreg = SPIx->I2SCFGR;
\ 00000018 A68B LDRH R6,[R4, #+28]
189
190 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
191 if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
\ 0000001A 0020 MOVS R0,#+0
\ 0000001C 8146 MOV R9,R0
\ 0000001E 2889 LDRH R0,[R5, #+8]
\ 00000020 0228 CMP R0,#+2
\ 00000022 02D1 BNE.N ??I2S_Init_1
192 {
193 i2sodd = (u16)0;
\ 00000024 4846 MOV R0,R9
194 i2sdiv = (u16)2;
\ 00000026 4146 MOV R1,R8
\ 00000028 2AE0 B.N ??I2S_Init_2
195 }
196 /* If the requested audio frequency is not the default, compute the prescaler */
197 else
198 {
199 /* Check the frame length (For the Prescaler computing) */
200 if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
\ ??I2S_Init_1:
\ 0000002A A888 LDRH R0,[R5, #+4]
\ 0000002C 0028 CMP R0,#+0
\ 0000002E 01D1 BNE.N ??I2S_Init_3
201 {
202 /* Packet length is 16 bits */
203 packetlength = 1;
\ 00000030 0127 MOVS R7,#+1
\ 00000032 00E0 B.N ??I2S_Init_4
204 }
205 else
206 {
207 /* Packet length is 32 bits */
208 packetlength = 2;
\ ??I2S_Init_3:
\ 00000034 4746 MOV R7,R8
209 }
210 /* Get System Clock frequency */
211 RCC_GetClocksFreq(&RCC_Clocks);
\ ??I2S_Init_4:
\ 00000036 6846 MOV R0,SP
\ 00000038 ........ _BLF RCC_GetClocksFreq,??RCC_GetClocksFreq??rT
212
213 /* Compute the Real divider depending on the MCLK output state with a flaoting point */
214 if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
\ 0000003C E888 LDRH R0,[R5, #+6]
\ 0000003E 5FF40071 MOVS R1,#+512
\ 00000042 8842 CMP R0,R1
\ 00000044 0098 LDR R0,[SP, #+0]
\ 00000046 08D1 BNE.N ??I2S_Init_5
215 {
216 /* MCLK output is enabled */
217 tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
\ 00000048 0A21 MOVS R1,#+10
\ 0000004A 4843 MULS R0,R1,R0
\ 0000004C 2989 LDRH R1,[R5, #+8]
\ 0000004E 0902 LSLS R1,R1,#+8
\ 00000050 B0FBF1F0 UDIV R0,R0,R1
\ 00000054 401D ADDS R0,R0,#+5
\ 00000056 80B2 UXTH R0,R0
\ 00000058 08E0 B.N ??I2S_Init_6
218 }
219 else
220 {
221 /* MCLK output is disabled */
222 tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
\ ??I2S_Init_5:
\ 0000005A 0A21 MOVS R1,#+10
\ 0000005C 4843 MULS R0,R1,R0
\ 0000005E 2989 LDRH R1,[R5, #+8]
\ 00000060 4F43 MULS R7,R1,R7
\ 00000062 7901 LSLS R1,R7,#+5
\ 00000064 B0FBF1F0 UDIV R0,R0,R1
\ 00000068 401D ADDS R0,R0,#+5
\ 0000006A 80B2 UXTH R0,R0
223 }
224
225 /* Remove the flaoting point */
226 tmp = tmp/10;
\ ??I2S_Init_6:
\ 0000006C 0A21 MOVS R1,#+10
\ 0000006E B0FBF1F0 UDIV R0,R0,R1
227
228 /* Check the parity of the divider */
229 i2sodd = (u16)(tmp & (u16)0x0001);
\ 00000072 0100 MOVS R1,R0
\ 00000074 0122 MOVS R2,#+1
\ 00000076 0A40 ANDS R2,R2,R1
230
231 /* Compute the i2sdiv prescaler */
232 i2sdiv = (u16)((tmp - i2sodd) / 2);
\ 00000078 801A SUBS R0,R0,R2
\ 0000007A 0100 MOVS R1,R0
\ 0000007C 4908 LSRS R1,R1,#+1
233
234 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
235 i2sodd = (u16) (i2sodd << 8);
\ 0000007E 1002 LSLS R0,R2,#+8
236 }
237
238 /* Test if the divider is 1 or 0 */
239 if ((i2sdiv < 2) || (i2sdiv > 0xFF))
\ ??I2S_Init_2:
\ 00000080 89B2 UXTH R1,R1
\ 00000082 0229 CMP R1,#+2
\ 00000084 03D3 BCC.N ??I2S_Init_7
\ 00000086 5FF48072 MOVS R2,#+256
\ 0000008A 9142 CMP R1,R2
\ 0000008C 01D3 BCC.N ??I2S_Init_8
240 {
241 /* Set the default values */
242 i2sdiv = 2;
\ ??I2S_Init_7:
\ 0000008E 4146 MOV R1,R8
243 i2sodd = 0;
\ 00000090 4846 MOV R0,R9
244 }
245
246 /* Write to SPIx I2SPR register the computed value */
247 SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);
\ ??I2S_Init_8:
\ 00000092 0843 ORRS R0,R0,R1
\ 00000094 E988 LDRH R1,[R5, #+6]
\ 00000096 0143 ORRS R1,R1,R0
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