📄 stm32f10x_fsmc.lst
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290 }
\ 0000007C 10BD POP {R4,PC} ;; return
291
292 /*******************************************************************************
293 * Function Name : FSMC_PCCARDInit
294 * Description : Initializes the FSMC PCCARD Bank according to the specified
295 * parameters in the FSMC_PCCARDInitStruct.
296 * Input : - FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
297 * structure that contains the configuration information for
298 * the FSMC PCCARD Bank.
299 * Output : None
300 * Return : None
301 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
302 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
303 {
304 /* Check the parameters */
305 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
306 assert_param(IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_PCCARDInitStruct->FSMC_AddressLowMapping));
307 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
308 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
309
310
311 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
312 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
313 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
314 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
315
316 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
317 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
318 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
319 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
320
321 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
322 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
323 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
324 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
325
326 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
327 FSMC_Bank4->PCR4 = (u32)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
328 FSMC_PCCARDInitStruct->FSMC_AddressLowMapping |
329 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
330 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
\ FSMC_PCCARDInit:
\ 00000000 .... LDR.N R1,??DataTable29 ;; 0xffffffffa00000a0
\ 00000002 0268 LDR R2,[R0, #+0]
\ 00000004 4368 LDR R3,[R0, #+4]
\ 00000006 1343 ORRS R3,R3,R2
\ 00000008 8268 LDR R2,[R0, #+8]
\ 0000000A 53EA4222 ORRS R2,R3,R2, LSL #+9
\ 0000000E C368 LDR R3,[R0, #+12]
\ 00000010 52EA4332 ORRS R2,R2,R3, LSL #+13
\ 00000014 0A60 STR R2,[R1, #+0]
331
332 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
333 FSMC_Bank4->PMEM4 = (u32)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
334 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
335 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
336 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000016 .... LDR.N R1,??DataTable23 ;; 0xffffffffa00000a8
\ 00000018 0269 LDR R2,[R0, #+16]
\ 0000001A 1268 LDR R2,[R2, #+0]
\ 0000001C 0369 LDR R3,[R0, #+16]
\ 0000001E 5B68 LDR R3,[R3, #+4]
\ 00000020 52EA0322 ORRS R2,R2,R3, LSL #+8
\ 00000024 0369 LDR R3,[R0, #+16]
\ 00000026 9B68 LDR R3,[R3, #+8]
\ 00000028 52EA0342 ORRS R2,R2,R3, LSL #+16
\ 0000002C 0369 LDR R3,[R0, #+16]
\ 0000002E DB68 LDR R3,[R3, #+12]
\ 00000030 52EA0362 ORRS R2,R2,R3, LSL #+24
\ 00000034 0A60 STR R2,[R1, #+0]
337
338 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
339 FSMC_Bank4->PATT4 = (u32)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
340 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
341 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
342 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000036 .... LDR.N R1,??DataTable24 ;; 0xffffffffa00000ac
\ 00000038 4269 LDR R2,[R0, #+20]
\ 0000003A 1268 LDR R2,[R2, #+0]
\ 0000003C 4369 LDR R3,[R0, #+20]
\ 0000003E 5B68 LDR R3,[R3, #+4]
\ 00000040 52EA0322 ORRS R2,R2,R3, LSL #+8
\ 00000044 4369 LDR R3,[R0, #+20]
\ 00000046 9B68 LDR R3,[R3, #+8]
\ 00000048 52EA0342 ORRS R2,R2,R3, LSL #+16
\ 0000004C 4369 LDR R3,[R0, #+20]
\ 0000004E DB68 LDR R3,[R3, #+12]
\ 00000050 52EA0362 ORRS R2,R2,R3, LSL #+24
\ 00000054 0A60 STR R2,[R1, #+0]
343
344 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
345 FSMC_Bank4->PIO4 = (u32)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
346 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
347 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
348 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000056 .... LDR.N R1,??DataTable25 ;; 0xffffffffa00000b0
\ 00000058 8269 LDR R2,[R0, #+24]
\ 0000005A 1268 LDR R2,[R2, #+0]
\ 0000005C 8369 LDR R3,[R0, #+24]
\ 0000005E 5B68 LDR R3,[R3, #+4]
\ 00000060 52EA0322 ORRS R2,R2,R3, LSL #+8
\ 00000064 8369 LDR R3,[R0, #+24]
\ 00000066 9B68 LDR R3,[R3, #+8]
\ 00000068 52EA0342 ORRS R2,R2,R3, LSL #+16
\ 0000006C 8069 LDR R0,[R0, #+24]
\ 0000006E C068 LDR R0,[R0, #+12]
\ 00000070 52EA0060 ORRS R0,R2,R0, LSL #+24
\ 00000074 0860 STR R0,[R1, #+0]
349 }
\ 00000076 7047 BX LR ;; return
350
351 /*******************************************************************************
352 * Function Name : FSMC_NORSRAMStructInit
353 * Description : Fills each FSMC_NORSRAMInitStruct member with its default value.
354 * Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
355 * structure which will be initialized.
356 * Output : None
357 * Return : None
358 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
359 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
360 {
\ FSMC_NORSRAMStructInit:
\ 00000000 10B5 PUSH {R4,LR}
361 /* Reset NOR/SRAM Init structure parameters values */
362 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
\ 00000002 0021 MOVS R1,#+0
\ 00000004 0160 STR R1,[R0, #+0]
363 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
\ 00000006 0222 MOVS R2,#+2
\ 00000008 4260 STR R2,[R0, #+4]
364 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
\ 0000000A 8160 STR R1,[R0, #+8]
365 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
\ 0000000C C160 STR R1,[R0, #+12]
366 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
\ 0000000E 0161 STR R1,[R0, #+16]
367 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
\ 00000010 4161 STR R1,[R0, #+20]
368 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
\ 00000012 8161 STR R1,[R0, #+24]
369 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
\ 00000014 C161 STR R1,[R0, #+28]
370 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
\ 00000016 D202 LSLS R2,R2,#+11
\ 00000018 0262 STR R2,[R0, #+32]
371 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
\ 0000001A 5200 LSLS R2,R2,#+1
\ 0000001C 4262 STR R2,[R0, #+36]
372 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
\ 0000001E 8162 STR R1,[R0, #+40]
373 FSMC_NORSRAMInitStruct->FSMC_AsyncWait = FSMC_AsyncWait_Disable;
\ 00000020 C162 STR R1,[R0, #+44]
374 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
\ 00000022 0163 STR R1,[R0, #+48]
375 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
\ 00000024 0F22 MOVS R2,#+15
\ 00000026 436B LDR R3,[R0, #+52]
\ 00000028 1A60 STR R2,[R3, #+0]
376 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
\ 0000002A 436B LDR R3,[R0, #+52]
\ 0000002C 5A60 STR R2,[R3, #+4]
377 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
\ 0000002E FF23 MOVS R3,#+255
\ 00000030 446B LDR R4,[R0, #+52]
\ 00000032 A360 STR R3,[R4, #+8]
378 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
\ 00000034 446B LDR R4,[R0, #+52]
\ 00000036 E260 STR R2,[R4, #+12]
379 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
\ 00000038 446B LDR R4,[R0, #+52]
\ 0000003A 2261 STR R2,[R4, #+16]
380 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
\ 0000003C 446B LDR R4,[R0, #+52]
\ 0000003E 6261 STR R2,[R4, #+20]
381 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
\ 00000040 446B LDR R4,[R0, #+52]
\ 00000042 A161 STR R1,[R4, #+24]
382 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
\ 00000044 846B LDR R4,[R0, #+56]
\ 00000046 2260 STR R2,[R4, #+0]
383 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
\ 00000048 846B LDR R4,[R0, #+56]
\ 0000004A 6260 STR R2,[R4, #+4]
384 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
\ 0000004C 846B LDR R4,[R0, #+56]
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