📄 stm32f10x_fsmc.lst
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\ 0000008C 4B60 STR R3,[R1, #+4]
191
192
193
194 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
195 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
\ 0000008E 816A LDR R1,[R0, #+40]
\ 00000090 B1F5804F CMP R1,#+16384
\ 00000094 1DD1 BNE.N ??FSMC_NORSRAMInit_1
196 {
197 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
198 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
199 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
200 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration));
201 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
202 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
203 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
204
205 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
206 (u32)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
207 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
208 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
209 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
210 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
211 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
212 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
\ 00000096 0168 LDR R1,[R0, #+0]
\ 00000098 .... LDR.N R2,??DataTable15 ;; 0xffffffffa0000104
\ 0000009A 836B LDR R3,[R0, #+56]
\ 0000009C 1B68 LDR R3,[R3, #+0]
\ 0000009E 846B LDR R4,[R0, #+56]
\ 000000A0 6468 LDR R4,[R4, #+4]
\ 000000A2 53EA0413 ORRS R3,R3,R4, LSL #+4
\ 000000A6 846B LDR R4,[R0, #+56]
\ 000000A8 A468 LDR R4,[R4, #+8]
\ 000000AA 53EA0423 ORRS R3,R3,R4, LSL #+8
\ 000000AE 846B LDR R4,[R0, #+56]
\ 000000B0 E468 LDR R4,[R4, #+12]
\ 000000B2 53EA0443 ORRS R3,R3,R4, LSL #+16
\ 000000B6 846B LDR R4,[R0, #+56]
\ 000000B8 2469 LDR R4,[R4, #+16]
\ 000000BA 53EA0453 ORRS R3,R3,R4, LSL #+20
\ 000000BE 846B LDR R4,[R0, #+56]
\ 000000C0 6469 LDR R4,[R4, #+20]
\ 000000C2 53EA0463 ORRS R3,R3,R4, LSL #+24
\ 000000C6 806B LDR R0,[R0, #+56]
\ 000000C8 8069 LDR R0,[R0, #+24]
\ 000000CA 1843 ORRS R0,R0,R3
\ 000000CC 42F82100 STR R0,[R2, R1, LSL #+2]
\ 000000D0 10BD POP {R4,PC}
213 }
214 else
215 {
216 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
\ ??FSMC_NORSRAMInit_1:
\ 000000D2 0068 LDR R0,[R0, #+0]
\ 000000D4 .... LDR.N R1,??DataTable15 ;; 0xffffffffa0000104
\ 000000D6 7FF07042 MVNS R2,#-268435456
\ 000000DA 41F82020 STR R2,[R1, R0, LSL #+2]
217 }
218 }
\ 000000DE 10BD POP {R4,PC} ;; return
219
220 /*******************************************************************************
221 * Function Name : FSMC_NANDInit
222 * Description : Initializes the FSMC NAND Banks according to the specified
223 * parameters in the FSMC_NANDInitStruct.
224 * Input : - FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
225 * structure that contains the configuration information for
226 * the FSMC NAND specified Banks.
227 * Output : None
228 * Return : None
229 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
230 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
231 {
\ FSMC_NANDInit:
\ 00000000 10B5 PUSH {R4,LR}
232 u32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
233
234 /* Check the parameters */
235 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
236 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
237 assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
238 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
239 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
240 assert_param( IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_NANDInitStruct->FSMC_AddressLowMapping));
241 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
242 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
243
244 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
245 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
246 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
247 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
248
249 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
250 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
251 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
252 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
253
254 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
255 tmppcr = (u32)FSMC_NANDInitStruct->FSMC_Waitfeature |
256 PCR_MemoryType_NAND |
257 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
258 FSMC_NANDInitStruct->FSMC_ECC |
259 FSMC_NANDInitStruct->FSMC_ECCPageSize |
260 FSMC_NANDInitStruct->FSMC_AddressLowMapping |
261 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
262 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
\ 00000002 4168 LDR R1,[R0, #+4]
\ 00000004 8268 LDR R2,[R0, #+8]
\ 00000006 0A43 ORRS R2,R2,R1
\ 00000008 C168 LDR R1,[R0, #+12]
\ 0000000A 1143 ORRS R1,R1,R2
\ 0000000C 0269 LDR R2,[R0, #+16]
\ 0000000E 0A43 ORRS R2,R2,R1
\ 00000010 4169 LDR R1,[R0, #+20]
\ 00000012 1143 ORRS R1,R1,R2
\ 00000014 8269 LDR R2,[R0, #+24]
\ 00000016 51EA4221 ORRS R1,R1,R2, LSL #+9
\ 0000001A C269 LDR R2,[R0, #+28]
\ 0000001C 51EA4231 ORRS R1,R1,R2, LSL #+13
\ 00000020 51F00801 ORRS R1,R1,#0x8
263
264 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
265 tmppmem = (u32)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
266 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
267 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
268 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000024 026A LDR R2,[R0, #+32]
\ 00000026 1268 LDR R2,[R2, #+0]
\ 00000028 036A LDR R3,[R0, #+32]
\ 0000002A 5B68 LDR R3,[R3, #+4]
\ 0000002C 52EA0322 ORRS R2,R2,R3, LSL #+8
\ 00000030 036A LDR R3,[R0, #+32]
\ 00000032 9B68 LDR R3,[R3, #+8]
\ 00000034 52EA0342 ORRS R2,R2,R3, LSL #+16
\ 00000038 036A LDR R3,[R0, #+32]
\ 0000003A DB68 LDR R3,[R3, #+12]
\ 0000003C 52EA0362 ORRS R2,R2,R3, LSL #+24
269
270 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
271 tmppatt = (u32)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
272 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
273 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
274 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
\ 00000040 436A LDR R3,[R0, #+36]
\ 00000042 1B68 LDR R3,[R3, #+0]
\ 00000044 446A LDR R4,[R0, #+36]
\ 00000046 6468 LDR R4,[R4, #+4]
\ 00000048 53EA0423 ORRS R3,R3,R4, LSL #+8
\ 0000004C 446A LDR R4,[R0, #+36]
\ 0000004E A468 LDR R4,[R4, #+8]
\ 00000050 53EA0443 ORRS R3,R3,R4, LSL #+16
\ 00000054 446A LDR R4,[R0, #+36]
\ 00000056 E468 LDR R4,[R4, #+12]
\ 00000058 53EA0463 ORRS R3,R3,R4, LSL #+24
275
276 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
\ 0000005C 0068 LDR R0,[R0, #+0]
\ 0000005E 1028 CMP R0,#+16
\ 00000060 06D1 BNE.N ??FSMC_NANDInit_0
277 {
278 /* FSMC_Bank2_NAND registers configuration */
279 FSMC_Bank2->PCR2 = tmppcr;
\ 00000062 .... LDR.N R0,??DataTable26 ;; 0xffffffffa0000060
\ 00000064 0160 STR R1,[R0, #+0]
280 FSMC_Bank2->PMEM2 = tmppmem;
\ 00000066 .... LDR.N R0,??DataTable17 ;; 0xffffffffa0000068
\ 00000068 0260 STR R2,[R0, #+0]
281 FSMC_Bank2->PATT2 = tmppatt;
\ 0000006A .... LDR.N R0,??DataTable18 ;; 0xffffffffa000006c
\ 0000006C 0360 STR R3,[R0, #+0]
\ 0000006E 10BD POP {R4,PC}
282 }
283 else
284 {
285 /* FSMC_Bank3_NAND registers configuration */
286 FSMC_Bank3->PCR3 = tmppcr;
\ ??FSMC_NANDInit_0:
\ 00000070 .... LDR.N R0,??DataTable27 ;; 0xffffffffa0000080
\ 00000072 0160 STR R1,[R0, #+0]
287 FSMC_Bank3->PMEM3 = tmppmem;
\ 00000074 .... LDR.N R0,??DataTable20 ;; 0xffffffffa0000088
\ 00000076 0260 STR R2,[R0, #+0]
288 FSMC_Bank3->PATT3 = tmppatt;
\ 00000078 .... LDR.N R0,??DataTable21 ;; 0xffffffffa000008c
\ 0000007A 0360 STR R3,[R0, #+0]
289 }
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