📄 stm32f10x_fsmc.lst
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96 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
\ 00000014 .... LDR.N R0,??DataTable17 ;; 0xffffffffa0000068
\ 00000016 0160 STR R1,[R0, #+0]
97 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
\ 00000018 .... LDR.N R0,??DataTable18 ;; 0xffffffffa000006c
\ 0000001A 0160 STR R1,[R0, #+0]
\ 0000001C 7047 BX LR
98 }
99 /* FSMC_Bank3_NAND */
100 else
101 {
102 /* Set the FSMC_Bank3 registers to their reset values */
103 FSMC_Bank3->PCR3 = 0x00000018;
\ ??FSMC_NANDDeInit_0:
\ 0000001E .... LDR.N R0,??DataTable27 ;; 0xffffffffa0000080
\ 00000020 0360 STR R3,[R0, #+0]
104 FSMC_Bank3->SR3 = 0x00000040;
\ 00000022 .... LDR.N R0,??DataTable6 ;; 0xffffffffa0000084
\ 00000024 0260 STR R2,[R0, #+0]
105 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
\ 00000026 .... LDR.N R0,??DataTable20 ;; 0xffffffffa0000088
\ 00000028 0160 STR R1,[R0, #+0]
106 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
\ 0000002A .... LDR.N R0,??DataTable21 ;; 0xffffffffa000008c
\ 0000002C 0160 STR R1,[R0, #+0]
107 }
108 }
\ 0000002E 7047 BX LR ;; return
109
110 /*******************************************************************************
111 * Function Name : FSMC_PCCARDDeInit
112 * Description : Deinitializes the FSMC PCCARD Bank registers to their default
113 * reset values.
114 * Input : None
115 * Output : None
116 * Return : None
117 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
118 void FSMC_PCCARDDeInit(void)
119 {
120 /* Set the FSMC_Bank4 registers to their reset values */
121 FSMC_Bank4->PCR4 = 0x00000018;
\ FSMC_PCCARDDeInit:
\ 00000000 .... LDR.N R0,??DataTable29 ;; 0xffffffffa00000a0
\ 00000002 1821 MOVS R1,#+24
\ 00000004 0160 STR R1,[R0, #+0]
122 FSMC_Bank4->SR4 = 0x00000000;
\ 00000006 .... LDR.N R0,??DataTable10 ;; 0xffffffffa00000a4
\ 00000008 0021 MOVS R1,#+0
\ 0000000A 0160 STR R1,[R0, #+0]
123 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
\ 0000000C 5FF0FC30 MOVS R0,#-50529028
\ 00000010 .... LDR.N R1,??DataTable23 ;; 0xffffffffa00000a8
\ 00000012 0860 STR R0,[R1, #+0]
124 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
\ 00000014 .... LDR.N R1,??DataTable24 ;; 0xffffffffa00000ac
\ 00000016 0860 STR R0,[R1, #+0]
125 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
\ 00000018 .... LDR.N R1,??DataTable25 ;; 0xffffffffa00000b0
\ 0000001A 0860 STR R0,[R1, #+0]
126 }
\ 0000001C 7047 BX LR ;; return
127
128 /*******************************************************************************
129 * Function Name : FSMC_NORSRAMInit
130 * Description : Initializes the FSMC NOR/SRAM Banks according to the
131 * specified parameters in the FSMC_NORSRAMInitStruct.
132 * Input : - FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
133 * structure that contains the configuration information for
134 * the FSMC NOR/SRAM specified Banks.
135 * Output : None
136 * Return : None
137 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
138 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
139 {
\ FSMC_NORSRAMInit:
\ 00000000 10B5 PUSH {R4,LR}
140 /* Check the parameters */
141 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
142 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
143 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
144 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
145 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
146 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
147 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
148 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
149 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
150 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
151 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
152 assert_param(IS_FSMC_ASYNC_WAIT(FSMC_NORSRAMInitStruct->FSMC_AsyncWait));
153 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
154 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
155 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
156 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
157 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
158 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
159 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
160 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
161
162 /* Bank1 NOR/SRAM control register configuration */
163 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
164 (u32)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
165 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
166 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
167 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
168 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
169 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
170 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
171 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
172 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
173 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
174 FSMC_NORSRAMInitStruct->FSMC_AsyncWait |
175 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
\ 00000002 0168 LDR R1,[R0, #+0]
\ 00000004 5FF02042 MOVS R2,#-1610612736
\ 00000008 4368 LDR R3,[R0, #+4]
\ 0000000A 8468 LDR R4,[R0, #+8]
\ 0000000C 1C43 ORRS R4,R4,R3
\ 0000000E C368 LDR R3,[R0, #+12]
\ 00000010 2343 ORRS R3,R3,R4
\ 00000012 0469 LDR R4,[R0, #+16]
\ 00000014 1C43 ORRS R4,R4,R3
\ 00000016 4369 LDR R3,[R0, #+20]
\ 00000018 2343 ORRS R3,R3,R4
\ 0000001A 8469 LDR R4,[R0, #+24]
\ 0000001C 1C43 ORRS R4,R4,R3
\ 0000001E C369 LDR R3,[R0, #+28]
\ 00000020 2343 ORRS R3,R3,R4
\ 00000022 046A LDR R4,[R0, #+32]
\ 00000024 1C43 ORRS R4,R4,R3
\ 00000026 436A LDR R3,[R0, #+36]
\ 00000028 2343 ORRS R3,R3,R4
\ 0000002A 846A LDR R4,[R0, #+40]
\ 0000002C 1C43 ORRS R4,R4,R3
\ 0000002E C36A LDR R3,[R0, #+44]
\ 00000030 2343 ORRS R3,R3,R4
\ 00000032 046B LDR R4,[R0, #+48]
\ 00000034 1C43 ORRS R4,R4,R3
\ 00000036 42F82140 STR R4,[R2, R1, LSL #+2]
176
177 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
\ 0000003A 8168 LDR R1,[R0, #+8]
\ 0000003C 0829 CMP R1,#+8
\ 0000003E 08D1 BNE.N ??FSMC_NORSRAMInit_0
178 {
179 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (u32)BCR_FACCEN_Set;
\ 00000040 0168 LDR R1,[R0, #+0]
\ 00000042 0B46 MOV R3,R1
\ 00000044 1446 MOV R4,R2
\ 00000046 54F82330 LDR R3,[R4, R3, LSL #+2]
\ 0000004A 53F04003 ORRS R3,R3,#0x40
\ 0000004E 42F82130 STR R3,[R2, R1, LSL #+2]
180 }
181
182 /* Bank1 NOR/SRAM timing register configuration */
183 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
184 (u32)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
185 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
186 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
187 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
188 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
189 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
190 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
\ ??FSMC_NORSRAMInit_0:
\ 00000052 0168 LDR R1,[R0, #+0]
\ 00000054 8900 LSLS R1,R1,#+2
\ 00000056 11F12041 ADDS R1,R1,#-1610612736
\ 0000005A 426B LDR R2,[R0, #+52]
\ 0000005C 1268 LDR R2,[R2, #+0]
\ 0000005E 436B LDR R3,[R0, #+52]
\ 00000060 5B68 LDR R3,[R3, #+4]
\ 00000062 52EA0312 ORRS R2,R2,R3, LSL #+4
\ 00000066 436B LDR R3,[R0, #+52]
\ 00000068 9B68 LDR R3,[R3, #+8]
\ 0000006A 52EA0322 ORRS R2,R2,R3, LSL #+8
\ 0000006E 436B LDR R3,[R0, #+52]
\ 00000070 DB68 LDR R3,[R3, #+12]
\ 00000072 52EA0342 ORRS R2,R2,R3, LSL #+16
\ 00000076 436B LDR R3,[R0, #+52]
\ 00000078 1B69 LDR R3,[R3, #+16]
\ 0000007A 52EA0352 ORRS R2,R2,R3, LSL #+20
\ 0000007E 436B LDR R3,[R0, #+52]
\ 00000080 5B69 LDR R3,[R3, #+20]
\ 00000082 52EA0362 ORRS R2,R2,R3, LSL #+24
\ 00000086 436B LDR R3,[R0, #+52]
\ 00000088 9B69 LDR R3,[R3, #+24]
\ 0000008A 1343 ORRS R3,R3,R2
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