📄 cpu_c.lst
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\ 000000D8 22E0 B.N ??CPU_IntSrcPrioSet_3
520 break;
521
522
523 /* ---------------- EXTERNAL INTERRUPT ---------------- */
524 default:
525 pos_max = CPU_INT_SRC_POS_MAX;
\ ??CPU_IntSrcPrioSet_1:
\ 000000DA .... LDR.N R0,??DataTable18 ;; 0xffffffffe000e004
\ 000000DC 0068 LDR R0,[R0, #+0]
\ 000000DE 4001 LSLS R0,R0,#+5
\ 000000E0 2130 ADDS R0,R0,#+33
\ 000000E2 C0B2 UXTB R0,R0
526 if (pos < pos_max) { /* See Note #3. */
\ 000000E4 8442 CMP R4,R0
\ 000000E6 1BD2 BCS.N ??CPU_IntSrcPrioSet_3
527 group = (pos - 16) / 4;
\ 000000E8 2700 MOVS R7,R4
\ 000000EA 103F SUBS R7,R7,#+16
\ 000000EC 3800 MOVS R0,R7
\ 000000EE 4010 ASRS R0,R0,#+1
\ 000000F0 17EB9070 ADDS R0,R7,R0, LSR #+30
\ 000000F4 0600 MOVS R6,R0
\ 000000F6 B610 ASRS R6,R6,#+2
\ 000000F8 F6B2 UXTB R6,R6
528 nbr = (pos - 16) % 4;
\ 000000FA F034 ADDS R4,R4,#+240
\ 000000FC B4EB8604 SUBS R4,R4,R6, LSL #+2
\ 00000100 E4B2 UXTB R4,R4
529
530 CPU_CRITICAL_ENTER();
\ 00000102 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
531 temp = CPU_REG_NVIC_PRIO(group);
\ 00000106 .... LDR.N R1,??DataTable19 ;; 0xffffffffe000e400
\ 00000108 11EB8602 ADDS R2,R1,R6, LSL #+2
\ 0000010C 1168 LDR R1,[R2, #+0]
532 temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
533 temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
534 CPU_REG_NVIC_PRIO(group) = temp;
\ 0000010E E300 LSLS R3,R4,#+3
\ 00000110 FF24 MOVS R4,#+255
\ 00000112 9C40 LSLS R4,R4,R3
\ 00000114 A143 BICS R1,R1,R4
\ 00000116 9D40 LSLS R5,R5,R3
\ 00000118 0D43 ORRS R5,R5,R1
\ 0000011A 1560 STR R5,[R2, #+0]
535 CPU_CRITICAL_EXIT();
\ 0000011C ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
536 }
537 break;
538 }
539 }
\ ??CPU_IntSrcPrioSet_3:
\ 00000120 BDE8F087 POP {R4-R10,PC} ;; return
540
541
542 /*
543 *********************************************************************************************************
544 * CPU_IntSrcPrioGet()
545 *
546 * Description : Get priority of an interrupt source.
547 *
548 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
549 *
550 * Return(s) : Priority of interrupt source. If the interrupt source specified is invalid, then
551 * DEF_INT_16S_MIN_VAL is returned.
552 *
553 * Caller(s) : Application.
554 *
555 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
556 *
557 * (2) See 'CPU_IntSrcPrioSet() Note #2'.
558 *
559 * (3) See 'CPU_IntSrcDis() Note #3'.
560 *********************************************************************************************************
561 */
562
\ In segment CODE, align 4, keep-with-next
563 CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
564 {
\ CPU_IntSrcPrioGet:
\ 00000000 F0B5 PUSH {R4-R7,LR}
\ 00000002 0500 MOVS R5,R0
565 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
566 CPU_SR cpu_sr;
567 #endif
568 CPU_INT08U group;
569 CPU_INT08U nbr;
570 CPU_INT08U pos_max;
571 CPU_INT16S prio;
572 CPU_INT32U prio_32;
573 CPU_INT32U temp;
574
575
576 switch (pos) {
\ 00000004 3B4C LDR.N R4,??CPU_IntSrcPrioGet_1 ;; 0xffffffffffff8000
\ 00000006 .... LDR.N R6,??DataTable15 ;; 0xffffffffe000ed18
\ 00000008 .... LDR.N R7,??DataTable16 ;; 0xffffffffe000ed20
\ 0000000A 0F28 CMP R0,#+15
\ 0000000C 4AD8 BHI.N ??CPU_IntSrcPrioGet_2
\ 0000000E DFE800F0 TBB [PC, R0]
\ ??CPU_IntSrcPrioGet_0:
\ 00000012 65080B0E DC8 +101,+8,+11,+14
\ 00000016 11182165 DC8 +17,+24,+33,+101
\ 0000001A 65656528 DC8 +101,+101,+101,+40
\ 0000001E 31653841 DC8 +49,+101,+56,+65
577 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
578 case CPU_INT_RSVD_07:
579 case CPU_INT_RSVD_08:
580 case CPU_INT_RSVD_09:
581 case CPU_INT_RSVD_10:
582 case CPU_INT_RSVD_13:
583 prio = DEF_INT_16S_MIN_VAL;
584 break;
585
586
587 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
588 case CPU_INT_RESET: /* Reset (see Note #2). */
589 prio = -3;
\ ??CPU_IntSrcPrioGet_3:
\ 00000022 7FF00204 MVNS R4,#+2
\ 00000026 59E0 B.N ??CPU_IntSrcPrioGet_4
590 break;
591
592 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
593 prio = -2;
\ ??CPU_IntSrcPrioGet_5:
\ 00000028 7FF00104 MVNS R4,#+1
\ 0000002C 56E0 B.N ??CPU_IntSrcPrioGet_4
594 break;
595
596 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
597 prio = -1;
\ ??CPU_IntSrcPrioGet_6:
\ 0000002E 5FF0FF34 MOVS R4,#-1
\ 00000032 53E0 B.N ??CPU_IntSrcPrioGet_4
598 break;
599
600
601 case CPU_INT_MEM: /* Memory management. */
602 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioGet_7:
\ 00000034 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
603 temp = CPU_REG_NVIC_SHPRI1;
\ 00000038 3668 LDR R6,[R6, #+0]
604 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
\ 0000003A F4B2 UXTB R4,R6
605 CPU_CRITICAL_EXIT();
\ 0000003C ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000040 4CE0 B.N ??CPU_IntSrcPrioGet_4
606 break;
607
608
609 case CPU_INT_BUSFAULT: /* Bus fault. */
610 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioGet_8:
\ 00000042 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
611 temp = CPU_REG_NVIC_SHPRI1;
\ 00000046 3668 LDR R6,[R6, #+0]
612 prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
\ 00000048 3100 MOVS R1,R6
\ 0000004A 090A LSRS R1,R1,#+8
\ 0000004C CCB2 UXTB R4,R1
613 CPU_CRITICAL_EXIT();
\ 0000004E ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000052 43E0 B.N ??CPU_IntSrcPrioGet_4
614 break;
615
616
617 case CPU_INT_USAGEFAULT: /* Usage fault. */
618 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioGet_9:
\ 00000054 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
619 temp = CPU_REG_NVIC_SHPRI1;
\ 00000058 3668 LDR R6,[R6, #+0]
620 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
\ 0000005A 3000 MOVS R0,R6
\ 0000005C 000C LSRS R0,R0,#+16
\ 0000005E C4B2 UXTB R4,R0
\ 00000060 3CE0 B.N ??CPU_IntSrcPrioGet_4
621 break;
622
623 case CPU_INT_SVCALL: /* SVCall. */
624 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioGet_10:
\ 00000062 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
625 temp = CPU_REG_NVIC_SHPRI2;
\ 00000066 .... LDR.N R1,??DataTable17 ;; 0xffffffffe000ed1c
\ 00000068 0E68 LDR R6,[R1, #+0]
626 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
\ 0000006A 3400 MOVS R4,R6
\ 0000006C 240E LSRS R4,R4,#+24
627 CPU_CRITICAL_EXIT();
\ 0000006E ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000072 33E0 B.N ??CPU_IntSrcPrioGet_4
628 break;
629
630 case CPU_INT_DBGMON: /* Debug monitor. */
631 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioGet_11:
\ 00000074 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
632 temp = CPU_REG_NVIC_SHPRI3;
\ 00000078 3E68 LDR R6,[R7, #+0]
633 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
\ 0000007A F4B2 UXTB R4,R6
634 CPU_CRITICAL_EXIT();
\ 0000007C ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000080 2CE0 B.N ??CPU_IntSrcPrioGet_4
635 break;
636
637 case CPU_INT_PENDSV: /* PendSV. ⌨️ 快捷键说明
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