📄 cpu_c.lst
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\ 00000098 43F82250 STR R5,[R3, R2, LSL #+2]
394 CPU_CRITICAL_EXIT();
\ 0000009C ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
395 }
396 break;
397 }
398 }
\ ??CPU_IntSrcEn_0:
\ 000000A0 30BD POP {R4,R5,PC} ;; return
\ 000000A2 00BF Nop
\ ??CPU_IntSrcEn_6:
\ 000000A4 00E100E0 DC32 0xffffffffe000e100
399
400
401 /*
402 *********************************************************************************************************
403 * CPU_IntSrcPrioSet()
404 *
405 * Description : Set priority of an interrupt source.
406 *
407 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
408 *
409 * prio Priority. Use a lower priority number for a higher priority.
410 *
411 * Return(s) : none.
412 *
413 * Caller(s) : Application.
414 *
415 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
416 *
417 * (2) Several interrupts priorities CANNOT be set :
418 *
419 * (a) Reset (always -3).
420 * (b) NMI (always -2).
421 * (c) Hard fault (always -1).
422 *
423 * (3) See 'CPU_IntSrcDis() Note #3'.
424 *********************************************************************************************************
425 */
426
\ In segment CODE, align 4, keep-with-next
427 void CPU_IntSrcPrioSet (CPU_INT08U pos,
428 CPU_INT08U prio)
429 {
\ CPU_IntSrcPrioSet:
\ 00000000 2DE9F047 PUSH {R4-R10,LR}
\ 00000004 0400 MOVS R4,R0
\ 00000006 0800 MOVS R0,R1
430 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
431 CPU_SR cpu_sr;
432 #endif
433 CPU_INT08U group;
434 CPU_INT08U nbr;
435 CPU_INT08U pos_max;
436 CPU_INT32U prio_32;
437 CPU_INT32U temp;
438
439
440 prio_32 = CPU_RevBits((CPU_INT08U)prio);
441 prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
\ 00000008 ........ _BLF CPU_RevBits,??CPU_RevBits??rT
\ 0000000C 0500 MOVS R5,R0
\ 0000000E 2D0E LSRS R5,R5,#+24
442
443 switch (pos) {
\ 00000010 .... LDR.N R6,??DataTable15 ;; 0xffffffffe000ed18
\ 00000012 7FF0FF00 MVNS R0,#+255
\ 00000016 8046 MOV R8,R0
\ 00000018 7FF47F00 MVNS R0,#+16711680
\ 0000001C 8146 MOV R9,R0
\ 0000001E 7FF07F40 MVNS R0,#-16777216
\ 00000022 8246 MOV R10,R0
\ 00000024 .... LDR.N R7,??DataTable16 ;; 0xffffffffe000ed20
\ 00000026 2000 MOVS R0,R4
\ 00000028 0F28 CMP R0,#+15
\ 0000002A 56D8 BHI.N ??CPU_IntSrcPrioSet_1
\ 0000002C DFE800F0 TBB [PC, R0]
\ ??CPU_IntSrcPrioSet_0:
\ 00000030 78787878 DC8 +120,+120,+120,+120
\ 00000034 08121E78 DC8 +8,+18,+30,+120
\ 00000038 78787829 DC8 +120,+120,+120,+41
\ 0000003C 35783F4A DC8 +53,+120,+63,+74
444 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
445 case CPU_INT_RSVD_07:
446 case CPU_INT_RSVD_08:
447 case CPU_INT_RSVD_09:
448 case CPU_INT_RSVD_10:
449 case CPU_INT_RSVD_13:
450 break;
451
452
453 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
454 case CPU_INT_RESET: /* Reset (see Note #2). */
455 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
456 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
457 break;
458
459 case CPU_INT_MEM: /* Memory management. */
460 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_2:
\ 00000040 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
461 temp = CPU_REG_NVIC_SHPRI1;
\ 00000044 3168 LDR R1,[R6, #+0]
462 temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
463 temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
464 CPU_REG_NVIC_SHPRI1 = temp;
\ 00000046 18EA0101 ANDS R1,R8,R1
\ 0000004A 0D43 ORRS R5,R5,R1
\ 0000004C 3560 STR R5,[R6, #+0]
465 CPU_CRITICAL_EXIT();
\ 0000004E ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000052 65E0 B.N ??CPU_IntSrcPrioSet_3
466 break;
467
468 case CPU_INT_BUSFAULT: /* Bus fault. */
469 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_4:
\ 00000054 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
470 temp = CPU_REG_NVIC_SHPRI1;
\ 00000058 3168 LDR R1,[R6, #+0]
471 temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
472 temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
473 CPU_REG_NVIC_SHPRI1 = temp;
\ 0000005A 7FF47F42 MVNS R2,#+65280
\ 0000005E 0A40 ANDS R2,R2,R1
\ 00000060 52EA0521 ORRS R1,R2,R5, LSL #+8
\ 00000064 3160 STR R1,[R6, #+0]
474 CPU_CRITICAL_EXIT();
\ 00000066 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 0000006A 59E0 B.N ??CPU_IntSrcPrioSet_3
475 break;
476
477 case CPU_INT_USAGEFAULT: /* Usage fault. */
478 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_5:
\ 0000006C ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
479 temp = CPU_REG_NVIC_SHPRI1;
\ 00000070 3168 LDR R1,[R6, #+0]
480 temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
481 temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
482 CPU_REG_NVIC_SHPRI1 = temp;
\ 00000072 19EA0101 ANDS R1,R9,R1
\ 00000076 51EA0541 ORRS R1,R1,R5, LSL #+16
\ 0000007A 3160 STR R1,[R6, #+0]
483 CPU_CRITICAL_EXIT();
\ 0000007C ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000080 4EE0 B.N ??CPU_IntSrcPrioSet_3
484 break;
485
486 case CPU_INT_SVCALL: /* SVCall. */
487 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_6:
\ 00000082 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
488 temp = CPU_REG_NVIC_SHPRI2;
\ 00000086 .... LDR.N R2,??DataTable17 ;; 0xffffffffe000ed1c
\ 00000088 1168 LDR R1,[R2, #+0]
489 temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
490 temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
491 CPU_REG_NVIC_SHPRI2 = temp;
\ 0000008A 1AEA0101 ANDS R1,R10,R1
\ 0000008E 51EA0561 ORRS R1,R1,R5, LSL #+24
\ 00000092 1160 STR R1,[R2, #+0]
492 CPU_CRITICAL_EXIT();
\ 00000094 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000098 42E0 B.N ??CPU_IntSrcPrioSet_3
493 break;
494
495 case CPU_INT_DBGMON: /* Debug monitor. */
496 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_7:
\ 0000009A ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
497 temp = CPU_REG_NVIC_SHPRI3;
\ 0000009E 3968 LDR R1,[R7, #+0]
498 temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
499 temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
500 CPU_REG_NVIC_SHPRI3 = temp;
\ 000000A0 18EA0101 ANDS R1,R8,R1
\ 000000A4 0D43 ORRS R5,R5,R1
\ 000000A6 3D60 STR R5,[R7, #+0]
501 CPU_CRITICAL_EXIT();
\ 000000A8 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 000000AC 38E0 B.N ??CPU_IntSrcPrioSet_3
502 break;
503
504 case CPU_INT_PENDSV: /* PendSV. */
505 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_8:
\ 000000AE ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
506 temp = CPU_REG_NVIC_SHPRI3;
\ 000000B2 3968 LDR R1,[R7, #+0]
507 temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
508 temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
509 CPU_REG_NVIC_SHPRI3 = temp;
\ 000000B4 19EA0101 ANDS R1,R9,R1
\ 000000B8 51EA0541 ORRS R1,R1,R5, LSL #+16
\ 000000BC 3960 STR R1,[R7, #+0]
510 CPU_CRITICAL_EXIT();
\ 000000BE ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 000000C2 2DE0 B.N ??CPU_IntSrcPrioSet_3
511 break;
512
513 case CPU_INT_SYSTICK: /* SysTick. */
514 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcPrioSet_9:
\ 000000C4 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
515 temp = CPU_REG_NVIC_SHPRI3;
\ 000000C8 3968 LDR R1,[R7, #+0]
516 temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
517 temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
518 CPU_REG_NVIC_SHPRI3 = temp;
\ 000000CA 1AEA0101 ANDS R1,R10,R1
\ 000000CE 51EA0561 ORRS R1,R1,R5, LSL #+24
\ 000000D2 3960 STR R1,[R7, #+0]
519 CPU_CRITICAL_EXIT();
\ 000000D4 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
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