📄 cpu_c.lst
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\ 00000056 2A60 STR R2,[R5, #+0]
285 CPU_CRITICAL_EXIT();
\ 00000058 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 0000005C 30BD POP {R4,R5,PC}
286 break;
287
288 case CPU_INT_SYSTICK: /* SysTick. */
289 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_4:
\ 0000005E ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
290 CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
\ 00000062 .... LDR.N R1,??DataTable8 ;; 0xffffffffe000e010
\ 00000064 0A68 LDR R2,[R1, #+0]
\ 00000066 0123 MOVS R3,#+1
\ 00000068 9A43 BICS R2,R2,R3
\ 0000006A 0A60 STR R2,[R1, #+0]
291 CPU_CRITICAL_EXIT();
\ 0000006C ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000070 30BD POP {R4,R5,PC}
292 break;
293
294
295 /* ---------------- EXTERNAL INTERRUPT ---------------- */
296 default:
297 pos_max = CPU_INT_SRC_POS_MAX;
\ ??CPU_IntSrcDis_5:
\ 00000072 .... LDR.N R0,??DataTable18 ;; 0xffffffffe000e004
\ 00000074 0068 LDR R0,[R0, #+0]
\ 00000076 4001 LSLS R0,R0,#+5
\ 00000078 2130 ADDS R0,R0,#+33
\ 0000007A C0B2 UXTB R0,R0
298 if (pos < pos_max) { /* See Note #3. */
\ 0000007C 8442 CMP R4,R0
\ 0000007E 12D2 BCS.N ??CPU_IntSrcDis_0
299 group = (pos - 16) / 32;
300 nbr = (pos - 16) % 32;
301
302 CPU_CRITICAL_ENTER();
\ 00000080 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
303 CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
\ 00000084 103C SUBS R4,R4,#+16
\ 00000086 2100 MOVS R1,R4
\ 00000088 0911 ASRS R1,R1,#+4
\ 0000008A 14EBD161 ADDS R1,R4,R1, LSR #+27
\ 0000008E 4911 ASRS R1,R1,#+5
\ 00000090 0A00 MOVS R2,R1
\ 00000092 D2B2 UXTB R2,R2
\ 00000094 044B LDR.N R3,??CPU_IntSrcDis_6 ;; 0xffffffffe000e180
\ 00000096 0125 MOVS R5,#+1
\ 00000098 B4EB4111 SUBS R1,R4,R1, LSL #+5
\ 0000009C 8D40 LSLS R5,R5,R1
\ 0000009E 43F82250 STR R5,[R3, R2, LSL #+2]
304 CPU_CRITICAL_EXIT();
\ 000000A2 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
305 }
306 break;
307 }
308 }
\ ??CPU_IntSrcDis_0:
\ 000000A6 30BD POP {R4,R5,PC} ;; return
\ ??CPU_IntSrcDis_6:
\ 000000A8 80E100E0 DC32 0xffffffffe000e180
309
310
311 /*
312 *********************************************************************************************************
313 * CPU_IntSrcEn()
314 *
315 * Description : Enable an interrupt source.
316 *
317 * Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
318 *
319 * Return(s) : none.
320 *
321 * Caller(s) : Application.
322 *
323 * Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
324 *
325 * (2) See 'CPU_IntSrcDis() Note #2'.
326 *
327 * (3) See 'CPU_IntSrcDis() Note #3'.
328 *********************************************************************************************************
329 */
330
\ In segment CODE, align 4, keep-with-next
331 void CPU_IntSrcEn (CPU_INT08U pos)
332 {
\ CPU_IntSrcEn:
\ 00000000 30B5 PUSH {R4,R5,LR}
\ 00000002 0400 MOVS R4,R0
333 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
334 CPU_SR cpu_sr;
335 #endif
336 CPU_INT08U group;
337 CPU_INT08U nbr;
338 CPU_INT08U pos_max;
339
340
341 switch (pos) {
\ 00000004 .... LDR.N R5,??DataTable7 ;; 0xffffffffe000ed24
\ 00000006 0328 CMP R0,#+3
\ 00000008 4AD9 BLS.N ??CPU_IntSrcEn_0
\ 0000000A 001F SUBS R0,R0,#+4
\ 0000000C 09D0 BEQ.N ??CPU_IntSrcEn_1
\ 0000000E 401E SUBS R0,R0,#+1
\ 00000010 10D0 BEQ.N ??CPU_IntSrcEn_2
\ 00000012 401E SUBS R0,R0,#+1
\ 00000014 17D0 BEQ.N ??CPU_IntSrcEn_3
\ 00000016 401E SUBS R0,R0,#+1
\ 00000018 0728 CMP R0,#+7
\ 0000001A 41D9 BLS.N ??CPU_IntSrcEn_0
\ 0000001C 0838 SUBS R0,R0,#+8
\ 0000001E 1BD0 BEQ.N ??CPU_IntSrcEn_4
\ 00000020 24E0 B.N ??CPU_IntSrcEn_5
342 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
343 case CPU_INT_RSVD_07:
344 case CPU_INT_RSVD_08:
345 case CPU_INT_RSVD_09:
346 case CPU_INT_RSVD_10:
347 case CPU_INT_RSVD_13:
348 break;
349
350
351 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
352 case CPU_INT_RESET: /* Reset (see Note #2). */
353 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
354 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
355 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
356 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
357 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
358 break;
359
360 case CPU_INT_MEM: /* Memory management. */
361 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcEn_1:
\ 00000022 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
362 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
\ 00000026 2968 LDR R1,[R5, #+0]
\ 00000028 51F48031 ORRS R1,R1,#0x10000
\ 0000002C 2960 STR R1,[R5, #+0]
363 CPU_CRITICAL_EXIT();
\ 0000002E ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000032 30BD POP {R4,R5,PC}
364 break;
365
366 case CPU_INT_BUSFAULT: /* Bus fault. */
367 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcEn_2:
\ 00000034 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
368 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
\ 00000038 2968 LDR R1,[R5, #+0]
\ 0000003A 51F40031 ORRS R1,R1,#0x20000
\ 0000003E 2960 STR R1,[R5, #+0]
369 CPU_CRITICAL_EXIT();
\ 00000040 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000044 30BD POP {R4,R5,PC}
370 break;
371
372 case CPU_INT_USAGEFAULT: /* Usage fault. */
373 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcEn_3:
\ 00000046 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
374 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
\ 0000004A 2968 LDR R1,[R5, #+0]
\ 0000004C 51F48021 ORRS R1,R1,#0x40000
\ 00000050 2960 STR R1,[R5, #+0]
375 CPU_CRITICAL_EXIT();
\ 00000052 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000056 30BD POP {R4,R5,PC}
376 break;
377
378 case CPU_INT_SYSTICK: /* SysTick. */
379 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcEn_4:
\ 00000058 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
380 CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
\ 0000005C .... LDR.N R1,??DataTable8 ;; 0xffffffffe000e010
\ 0000005E 0A68 LDR R2,[R1, #+0]
\ 00000060 52F00102 ORRS R2,R2,#0x1
\ 00000064 0A60 STR R2,[R1, #+0]
381 CPU_CRITICAL_EXIT();
\ 00000066 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 0000006A 30BD POP {R4,R5,PC}
382 break;
383
384
385 /* ---------------- EXTERNAL INTERRUPT ---------------- */
386 default:
387 pos_max = CPU_INT_SRC_POS_MAX;
\ ??CPU_IntSrcEn_5:
\ 0000006C .... LDR.N R0,??DataTable18 ;; 0xffffffffe000e004
\ 0000006E 0068 LDR R0,[R0, #+0]
\ 00000070 4001 LSLS R0,R0,#+5
\ 00000072 2130 ADDS R0,R0,#+33
\ 00000074 C0B2 UXTB R0,R0
388 if (pos < pos_max) { /* See Note #3. */
\ 00000076 8442 CMP R4,R0
\ 00000078 12D2 BCS.N ??CPU_IntSrcEn_0
389 group = (pos - 16) / 32;
390 nbr = (pos - 16) % 32;
391
392 CPU_CRITICAL_ENTER();
\ 0000007A ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
393 CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
\ 0000007E 103C SUBS R4,R4,#+16
\ 00000080 2100 MOVS R1,R4
\ 00000082 0911 ASRS R1,R1,#+4
\ 00000084 14EBD161 ADDS R1,R4,R1, LSR #+27
\ 00000088 4911 ASRS R1,R1,#+5
\ 0000008A 0A00 MOVS R2,R1
\ 0000008C D2B2 UXTB R2,R2
\ 0000008E 054B LDR.N R3,??CPU_IntSrcEn_6 ;; 0xffffffffe000e100
\ 00000090 0125 MOVS R5,#+1
\ 00000092 B4EB4111 SUBS R1,R4,R1, LSL #+5
\ 00000096 8D40 LSLS R5,R5,R1
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