📄 cpu_c.lst
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\ 00000020 05D3 BCC.N ??CPU_BitBandClr_1
\ 00000022 .... LDR.N R3,??DataTable3 ;; 0x40100000
\ 00000024 9842 CMP R0,R3
\ 00000026 02D2 BCS.N ??CPU_BitBandClr_1
142 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
143 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
144
145 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
\ 00000028 5FF08440 MOVS R0,#+1107296256
\ 0000002C 0A50 STR R2,[R1, R0]
146 }
147 }
\ ??CPU_BitBandClr_1:
\ 0000002E 7047 BX LR ;; return
148
149
150 /*
151 *********************************************************************************************************
152 * CPU_BitBandClr()
153 *
154 * Description : Set bit in bit-band region.
155 *
156 * Argument(s) : addr Byte address in memory space.
157 *
158 * bit_nbr Bit number in byte.
159 *
160 * Return(s) : none.
161 *
162 * Caller(s) : Application.
163 *
164 * Note(s) : none.
165 *********************************************************************************************************
166 */
167
\ In segment CODE, align 4, keep-with-next
168 void CPU_BitBandSet (CPU_ADDR addr,
169 CPU_INT08U bit_nbr)
170 {
171 CPU_ADDR bit_word_off;
172 CPU_ADDR bit_word_addr;
173
174
175 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
176 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
\ CPU_BitBandSet:
\ 00000000 8900 LSLS R1,R1,#+2
\ 00000002 11EB4011 ADDS R1,R1,R0, LSL #+5
\ 00000006 0122 MOVS R2,#+1
\ 00000008 B0F1005F CMP R0,#+536870912
\ 0000000C 06D3 BCC.N ??CPU_BitBandSet_0
\ 0000000E .... LDR.N R3,??DataTable2 ;; 0x20100000
\ 00000010 9842 CMP R0,R3
\ 00000012 03D2 BCS.N ??CPU_BitBandSet_0
177 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO) * 32) + (bit_nbr * 4);
178 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
179
180 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
\ 00000014 5FF00850 MOVS R0,#+570425344
\ 00000018 0A50 STR R2,[R1, R0]
\ 0000001A 7047 BX LR
181
182 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
183 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
\ ??CPU_BitBandSet_0:
\ 0000001C B0F1804F CMP R0,#+1073741824
\ 00000020 05D3 BCC.N ??CPU_BitBandSet_1
\ 00000022 .... LDR.N R3,??DataTable3 ;; 0x40100000
\ 00000024 9842 CMP R0,R3
\ 00000026 02D2 BCS.N ??CPU_BitBandSet_1
184 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
185 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
186
187 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
\ 00000028 5FF08440 MOVS R0,#+1107296256
\ 0000002C 0A50 STR R2,[R1, R0]
188 }
189 }
\ ??CPU_BitBandSet_1:
\ 0000002E 7047 BX LR ;; return
190
191
192 /*
193 *********************************************************************************************************
194 * CPU_IntSrcDis()
195 *
196 * Description : Disable an interrupt source.
197 *
198 * Argument(s) : pos Position of interrupt vector in interrupt table :
199 *
200 * 0 Invalid (see Note #1a).
201 * 1 Invalid (see Note #1b).
202 * 2 Non-maskable interrupt.
203 * 3 Hard Fault.
204 * 4 Memory Management.
205 * 5 Bus Fault.
206 * 6 Usage Fault.
207 * 7-10 Reserved.
208 * 11 SVCall
209 * 12 Debug monitor.
210 * 13 Reserved
211 * 14 PendSV.
212 * 15 SysTick.
213 * 16+ External Interrupt.
214 *
215 * Return(s) : none.
216 *
217 * Caller(s) : Application.
218 *
219 * Note(s) : (1) Several table positions do not contain interrupt sources :
220 *
221 * (a) Position 0 contains the stack pointer.
222 * (b) Positions 7-10, 13 are reserved.
223 *
224 * (2) Several interrupts cannot be disabled/enabled :
225 *
226 * (a) Reset.
227 * (b) NMI.
228 * (c) Hard fault.
229 * (d) SVCall.
230 * (e) Debug monitor.
231 * (f) PendSV.
232 *
233 * (3) The maximum Cortex-M3 table position is 256. A particular Cortex-M3 may have fewer
234 * than 240 external exceptions and, consequently, fewer than 256 table positions.
235 * This function assumes that the specified table position is valid if the interrupt
236 * controller type register's INTLINESNUM field is large enough so that the position
237 * COULD be valid.
238 *********************************************************************************************************
239 */
240
\ In segment CODE, align 4, keep-with-next
241 void CPU_IntSrcDis (CPU_INT08U pos)
242 {
\ CPU_IntSrcDis:
\ 00000000 30B5 PUSH {R4,R5,LR}
\ 00000002 0400 MOVS R4,R0
243 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
244 CPU_SR cpu_sr;
245 #endif
246 CPU_INT08U group;
247 CPU_INT08U pos_max;
248 CPU_INT08U nbr;
249
250
251 switch (pos) {
\ 00000004 .... LDR.N R5,??DataTable7 ;; 0xffffffffe000ed24
\ 00000006 0328 CMP R0,#+3
\ 00000008 4DD9 BLS.N ??CPU_IntSrcDis_0
\ 0000000A 001F SUBS R0,R0,#+4
\ 0000000C 09D0 BEQ.N ??CPU_IntSrcDis_1
\ 0000000E 401E SUBS R0,R0,#+1
\ 00000010 11D0 BEQ.N ??CPU_IntSrcDis_2
\ 00000012 401E SUBS R0,R0,#+1
\ 00000014 19D0 BEQ.N ??CPU_IntSrcDis_3
\ 00000016 401E SUBS R0,R0,#+1
\ 00000018 0728 CMP R0,#+7
\ 0000001A 44D9 BLS.N ??CPU_IntSrcDis_0
\ 0000001C 0838 SUBS R0,R0,#+8
\ 0000001E 1ED0 BEQ.N ??CPU_IntSrcDis_4
\ 00000020 27E0 B.N ??CPU_IntSrcDis_5
252 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
253 case CPU_INT_RSVD_07:
254 case CPU_INT_RSVD_08:
255 case CPU_INT_RSVD_09:
256 case CPU_INT_RSVD_10:
257 case CPU_INT_RSVD_13:
258 break;
259
260
261 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
262 case CPU_INT_RESET: /* Reset (see Note #2). */
263 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
264 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
265 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
266 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
267 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
268 break;
269
270 case CPU_INT_MEM: /* Memory management. */
271 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_1:
\ 00000022 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
272 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
\ 00000026 2968 LDR R1,[R5, #+0]
\ 00000028 7FF48032 MVNS R2,#+65536
\ 0000002C 0A40 ANDS R2,R2,R1
\ 0000002E 2A60 STR R2,[R5, #+0]
273 CPU_CRITICAL_EXIT();
\ 00000030 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000034 30BD POP {R4,R5,PC}
274 break;
275
276 case CPU_INT_BUSFAULT: /* Bus fault. */
277 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_2:
\ 00000036 ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
278 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
\ 0000003A 2968 LDR R1,[R5, #+0]
\ 0000003C 7FF40032 MVNS R2,#+131072
\ 00000040 0A40 ANDS R2,R2,R1
\ 00000042 2A60 STR R2,[R5, #+0]
279 CPU_CRITICAL_EXIT();
\ 00000044 ........ _BLF CPU_SR_Restore,??CPU_SR_Restore??rT
\ 00000048 30BD POP {R4,R5,PC}
280 break;
281
282 case CPU_INT_USAGEFAULT: /* Usage fault. */
283 CPU_CRITICAL_ENTER();
\ ??CPU_IntSrcDis_3:
\ 0000004A ........ _BLF CPU_SR_Save,??CPU_SR_Save??rT
284 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
\ 0000004E 2968 LDR R1,[R5, #+0]
\ 00000050 7FF48022 MVNS R2,#+262144
\ 00000054 0A40 ANDS R2,R2,R1
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