encoder_8b10b.vhd

可编程器件厂商Altera出品的8b10b编码器源代码

-- (C) COPYRIGHT PLD APPLICATIONS 1998-2000, ALL RIGHTS RESERVED
-- BUILD G8B10B_0100
library ieee;
use ieee.std_logic_1164.all;
entity encoder_8b10b is
	port
		(
		clk			: in	std_logic;		   				
		rstn		: in	std_logic;					   	
		
		frame_in	: in	std_logic;					   	
		data_in		: in	std_logic_vector (7 downto 0);	
		kchar_in	: in	std_logic_vector (3 downto 0);	
		
		frame_enc	: out	std_logic;					   	
		data_enc	: out	std_logic_vector (9 downto 0)  	
		);
end encoder_8b10b;
architecture structural of encoder_8b10b is
	component encoder_lut
	port(
		address : in std_logic_vector(7 downto 0);
		inclock : in std_logic;
		outclock : in std_logic;
		q : out std_logic_vector(15 downto 0));
	end component;
	
	signal data_lut_r,kchar_lut_r				: std_logic_vector (15 downto 0); 
	signal kchar_r								: std_logic_vector (3 downto 0);
	signal kchar_enable_r,frame_in_r,frame_r	: std_logic;
	
	
	signal disparity_r							: std_logic;
	signal code_lut								: std_logic_vector (15 downto 0);
begin
	
	
	
	
	
	
	
	
	
	
	
	enclut : encoder_lut port map (address => data_in, inclock => clk, outclock => clk, q=>data_lut_r);
	
	process (clk,rstn)
	begin
		if rstn='0' then
			frame_in_r <='0';
			frame_r <='0';
			kchar_r <=(others=>'0');
			kchar_enable_r <='0';
			kchar_lut_r <=(others=>'0');
		elsif rising_edge (clk) then
			
			frame_in_r <=frame_in;
			frame_r <=frame_in_r;
			kchar_r <=kchar_in;
			
			
			if kchar_r(3 downto 2)="00" then kchar_enable_r <='0';	
			else kchar_enable_r <='1';						 		
			end if;
			
			
			case kchar_r is
				when "0100" => kchar_lut_r <="1111100001010111"; 
				when "0101" => kchar_lut_r <="1111100001011011"; 
				when "0110" => kchar_lut_r <="1111100001011101"; 
				when "0111" => kchar_lut_r <="1111100001011110"; 
				when "1000" => kchar_lut_r <="1111010010111100"; 
				when "1001" => kchar_lut_r <="0101101001111100"; 
				when "1010" => kchar_lut_r <="0101011010111100"; 
				when "1011" => kchar_lut_r <="0100111100111100"; 
				when "1100" => kchar_lut_r <="1110110100111100"; 
				when "1101" => kchar_lut_r <="0110100101111100"; 
				when "1110" => kchar_lut_r <="0110010110111100"; 
				when "1111" => kchar_lut_r <="1111100001111100"; 
				when others => kchar_lut_r <=(others=>'0');
			end case;
		end if;
	end process;
	
	
	
	
	
	
	
	code_lut <=kchar_lut_r when kchar_enable_r='1' else data_lut_r;
	
	process (clk,rstn)
	begin
		if rstn='0' then
			frame_enc <='0';
			disparity_r <='0';
			data_enc <=(others=>'0');
		elsif rising_edge (clk) then
			frame_enc <=frame_r;
			
			
			if frame_r='0' then disparity_r <='0';						
			elsif code_lut(15)='0' then disparity_r <=not disparity_r;	
			end if;
			
			
			if disparity_r='0' then data_enc <=code_lut(9 downto 0);
			else
				if code_lut(14)='1' then data_enc <=code_lut(13 downto 10) & not code_lut(5 downto 0);
				else data_enc <=code_lut(13 downto 10) & code_lut(5 downto 0);
				end if;
			end if;
		end if;
	end process;
	
end structural;