secnand.h

samsung 最新芯片2450 的测试程序.

#ifndef __SECNAND_H__
#define __SECNAND_H__


#ifdef __cplusplus
extern "C" {
#endif

/* Option constants for bizarre disfunctionality and real
*  features
*/
/* Chip can not auto increment pages */
#define NAND_NO_AUTOINCR	0x00000001
/* Buswitdh is 16 bit */
#define NAND_BUSWIDTH_16	0x00000002
/* Device supports partial programming without padding */
#define NAND_NO_PADDING		0x00000004
/* Chip has cache program function */
#define NAND_CACHEPRG		0x00000008
/* Chip has copy back function */
#define NAND_COPYBACK		0x00000010
/* AND Chip which has 4 banks and a confusing page / block
 * assignment. See Renesas datasheet for further information */
#define NAND_IS_AND		0x00000020
/* Chip has a array of 4 pages which can be read without
 * additional ready /busy waits */
#define NAND_4PAGE_ARRAY	0x00000040
/* Chip requires that BBT is periodically rewritten to prevent
 * bits from adjacent blocks from 'leaking' in altering data.
 * This happens with the Renesas AG-AND chips, possibly others.  */
#define BBT_AUTO_REFRESH	0x00000080

/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS \
	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)



/*
 * Standard NAND flash commands
 */
#define CMD_READ0				0x00
#define CMD_READ1				0x01

#define CMD_PAGEPROG			0x80
#define CMD_PAGEPROG_2CYCLE		0x10

#define CMD_READOOB				0x50
#define CMD_ERASE1				0x60
#define CMD_STATUS				0x70
#define CMD_STATUS_MULTI		0x71

#define CMD_READID				0x90
#define CMD_ERASE2				0xd0
#define CMD_RESET				0xff

/* Extended commands for large page devices */
#define CMD_READ0_2CYCLE		0x30
#define CMD_CACHEDPROG				0x15
#define	CMD_RANDOM_DATA_OUT_1ST_CYCLE	0x05
#define	CMD_RANDOM_DATA_OUT_2ND_CYCLE	0xE0
#define	CMD_RANDOM_DATA_IN			0x85



/*
 * NAND Flash Manufacturer ID Codes
 */
#define MAN_ID_TOSHIBA	0x98
#define MAN_ID_SAMSUNG	0xec
#define MAN_ID_FUJITSU	0x04
#define MAN_ID_NATIONAL	0x8f
#define MAN_ID_RENESAS	0x07
#define MAN_ID_STMICRO	0x20
#define MAN_ID_HYNIX    0xad

/**
 * struct nand_flash_dev - NAND Flash Device ID Structure
 *
 * @name:  	Identify the device type
 * @id:   	device ID code
 * @pagesize:  	Pagesize in bytes. Either 256 or 512 or 0
 *		If the pagesize is 0, then the real pagesize
 *		and the eraseize are determined from the
 *		extended id bytes in the chip
 * @erasesize: 	Size of an erase block in the flash device.
 * @chipsize:  	Total chipsize in Mega Bytes
 * @options:	Bitfield to store chip relevant options
 */

/**
 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 * @name:	Manufacturer name
 * @id: 	manufacturer ID code of device.
*/
struct nand_manufacturers {
	int id;
	char * name;
};


struct CurNandInfo {
	char *name;
	int id;
	unsigned long pagesize;
	unsigned long chipsize;
	unsigned long erasesize;
	unsigned long options;
};


extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];


/**
 * struct nand_flash_dev - NAND Flash Device ID Structure
 *
 * @name:  	Identify the device type
 * @id:   	device ID code
 * @pagesize:  	Pagesize in bytes. Either 256 or 512 or 0
 *		If the pagesize is 0, then the real pagesize
 *		and the eraseize are determined from the
 *		extended id bytes in the chip
 * @erasesize: 	Size of an erase block in the flash device.
 * @chipsize:  	Total chipsize in Mega Bytes
 * @options:	Bitfield to store chip relevant options
 */
struct nand_flash_dev {
	char *name;
	int id;
	unsigned long pagesize;
	unsigned long chipsize;
	unsigned long erasesize;
	unsigned long options;
};




#define		NUM_ID				8
#define		SIZE_OF_MAN_NAME	64
#define		SLC_TYPE			0				
#define		MLC_TYPE			1	
#define		N_ROW_ADDRESS		8				


typedef struct st_NandInfo
{
	unsigned int uNId;
	unsigned char uId[NUM_ID];
	char sName[SIZE_OF_MAN_NAME];
	unsigned int uNandSize;
	unsigned int uColCycle;     //PageAddr      
	unsigned int uRowCycle;		//Nth PageAddr  
	unsigned int uAddrCycle;	//uAddrCycle = uColCycle + uRowCycle
	unsigned int uIsMLC;
	unsigned int uAddrCycleNum;
	unsigned int uBlockShift;
	unsigned char uRowAddr[N_ROW_ADDRESS];
	unsigned int u512BytesPerPage;
	
	unsigned int uCurBlock;
	unsigned int uCurPage;
	unsigned int uPagesPerBlock;
	
	//3rd ID data
	unsigned int uIntChipNum;
	unsigned int uCellType;
	unsigned int uNSimProgPages; //Num of Simultaneously Prgrammed Pages
	unsigned int uInterleaveProg;//Interleave Program Between multiple chips
	unsigned int uCacheProg;    //Cache Program
	
	//4th ID Data
	unsigned int uPageSize;
	unsigned int uBlockSize;
	unsigned int uRedundantAreaSize;
	unsigned int uOrganization;
	unsigned int uSerialAccessMin;
		
	//5th ID Data
	unsigned int uPlaneNum;
	unsigned int uPlaneSize;	
		
}NANDINFO;

void __irq tNFCon_Int(void);
void InitNFC(void);
void ReadID(void);
U8 ReadNandStatus(void);
int EraseBlock(unsigned int uBlock);
void TestNFC(void);
void PrintSubMessage(void);
void TestReadPage(void);
void TestWritePage(void);
int WritePage(unsigned char* pWBuf,unsigned int  uBlock, unsigned int uPage);
unsigned int  NAND_Write2048Page_8BitValid( unsigned char *pBuffer, unsigned int uBlock, unsigned int uPage);
void TestEraseBlock(void);
void WriteDramImage2Nand(void);
void ReadNandImage2Dram(void);
unsigned int SetLock(unsigned int uStartBlock, unsigned int uEndBlock, unsigned int uIsSoftLock);
void Test_Lock(void);
void ClearSoftLock(void);



#ifdef __cplusplus
}
#endif

#endif //__SECNAND_H__