dmc.c

samsung 最新芯片2450 的测试程序.

	
	test = (*(unsigned int *)(0x31000000));

	rGPADAT |= (0x1<<13);
	printf("\n test = %x",test);
	Delay(10);
	
	//printf("\n data = %x",(*(unsigned int *)(0x31000000)));
	//printf("\n data = %x",(*(unsigned int *)(0x31002000)));	
	
	
	
}

void SDR_ModeTest_BSTOP(void)
{
	volatile unsigned int *pt;
	volatile unsigned int data;
	int memError=0;
	int test;
		
	rBANKCON1 |= (1<<7)|(1<<5); // BSTOP Enable & Auto Precharge disable to see a precharge command out
	//GPIO trigger set-up
	
	//rBANKCON1 &= ~(1<<5);
	
	rGPADAT &= ~(0x1<<13);
	test = (*(unsigned int *)(0x31000000));
	//printf("\n test = %x",test);
	//printf("\n data = %x",(*(unsigned int *)(0x31000000)));
	//printf("\n data = %x",(*(unsigned int *)(0x31002000)));		
	rGPADAT |= (0x1<<13);	
	Delay(1);
}

void SDR_ModeTest_WBUF(void)
{
	volatile unsigned int *pt;
	volatile unsigned int data;
	int memError=0;
	int test;

	rBANKCON1 |= (1<<5); // Auto Precharge disable to see a precharge command out

	//rTIMEOUT = 0xffff;
	rGPFDAT |= (0x1<<0);
	(*(unsigned int *)(0x31000000)) = 0xaaaaaaaa;	
	//Delay(1);
	rGPFDAT &= ~(0x1<<0);
}

void SDR_ModeTest_tRP(void)
{
	volatile unsigned int *pt;
	volatile unsigned int data;
	int memError=0;
	int test1,test2;
	
	(*(unsigned int *)(0x31000000)) = 0xaaaaaaaa;	
	//GPIO trigger set-up
	rGPADAT &= ~(0x1<<13);

	//rBANKCFG &= ~(0x3<<6);
	
	rBANKCON1 |= (1<<5); // Auto Precharge disable to see a precharge command out

	//rBANKCFG |= (0x1<<0);

	//(*(unsigned int *)(0x31000000)) = 0xaaaa5555;			
	//(*(unsigned int *)(0x31002000)) = 0x12345678;	

	test1 = (*(unsigned int *)(0x31000000));
	test2 = (*(unsigned int *)(0x31002000));
	
	rGPADAT |= (0x1<<13);
	printf("\n test = %x",test1);
	printf("\n data = %x",(*(unsigned int *)(0x31000000)));
	printf("\n data = %x",(*(unsigned int *)(0x31002000)));	

	Delay(1);
}

void SDR_ModeTest_tARFC(void)
{
	volatile unsigned int *pt;
	volatile unsigned int data;
	int memError=0;

	//GPIO trigger set-up
	rGPADAT &= ~(0x1<<13);

	//rBANKCFG &= ~(0x3<<6);
	
	rBANKCON1 |= (1<<5); // Auto Precharge disable to see a precharge command out

	//rBANKCFG |= (0x1<<0);

	(*(unsigned int *)(0x31000000)) = 0xaaaa5555;			
	(*(unsigned int *)(0x31000004)) = 0xaaaa5555;		

	(*(unsigned int *)(0x31000008)) = 0x12345678;			
	(*(unsigned int *)(0x3100000c)) = 0x12345678;		
	//(*(unsigned int *)(0x31002000)) = 0x12345678;	

	//rBANKCON1 |= (1<<7); // Bstop is only available for DDR
	//rBANKCON2 = rBANKCON2 & ~(0x3<<4) |(0x2<<4); // CAS latency 2 Fail
	
	Delay(10);
	//printf("\n data = %x",(*(unsigned int *)(0x31000000)));
	//printf("\n data = %x",(*(unsigned int *)(0x31002000)));

	rGPADAT |= (0x1<<13);
}

void SDR_PerformanceTest_DMA(void)
{
	U32	*SrcAddr, *DstAddr, i;
	U32 transtime;

	dma_done_DMC =0;

	//rBANKCFG |= (1<<6);
	/*
	rBANKCON1 |= (1<<7) | (1<<6) | (1<<4);
	rBANKCON1 &= ~((1<<6)|(1<<7));
	*/
	
	rGPFDAT |= (0x1<<0);

	SrcAddr = (U32 *)(_NONCACHE_STARTADDRESS+0x00000000);
	//DstAddr = (U32 *)(_NONCACHE_STARTADDRESS+0x01000000);

	for (i=0; i<0x100000 ;i+=4)
	*SrcAddr++ = 0x12345678;
	
	printf("\n1MB Mem to Mem data transfer\n");
	
	pISR_DMA=(int)DmaDone_DMC;
	rINTMSK&=~(BIT_DMA);
	rINTSUBMSK&=~(BIT_SUB_DMA0);
	
	rDISRC0=0x31000000;
	rDISRCC0=(0<<1)|(0<<0); // AHB, INC
	rDIDST0=0x31200000;
	rDIDSTC0=(0<<1)|(0<<0); // AHB, INC
	rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<22)|(2<<20)|(0x10000);			
	rDMAREQSEL0=0; //S/W request mode

	//StartStopwatch();
	rGPFDAT &= ~(0x1<<0);
	
	rDMASKTRIG0=(1<<1)|1; //DMA on, SW_TRIG

	while(!dma_done_DMC);

	rGPFDAT |= (0x1<<0);
	//transtime = EndStopwatch();
	//CalculationBPS_HSMMC(transtime);
	
	printf("\nDMA Transfer Done\n");
}

void SDR_PerformanceTest_ForLoop(void)
{
	U32	*StartAddr, *EndAddr, i;

	printf("\n1MB Mem to Mem data transfer Using For Loop\n");	

	/*
	rBANKCFG |= (1<<6);
	rBANKCON1 |= (1<<7) | (1<<6) | (1<<4);
	*/
	
	StartAddr = (U32 *)(_NONCACHE_STARTADDRESS);
	EndAddr = (U32 *)(_NONCACHE_STARTADDRESS+0x100000);

	for (i=0; i<(0x100000) ;i+=4)
	*StartAddr++ = 0x12345678;

	rGPFDAT |= (0x1<<0);
	Delay(1);
	rGPFDAT &= ~(0x1<<0);		
	
	CopybyForLoop(0x31000000, 0x31200000, 0x40000);

	rGPFDAT |= (0x1<<0);
}

void CopybyForLoop(U32 sa, U32 da, U32 words)
{
	U32 i;	
	for (i=0; i<words; i++)
		*(U32 *)(da+i*4) = *(U32 *)(sa+i*4);
	printf("");
}

void SDR_PerformanceTest_Memcpy(void)
{
	U32	*srcAddr, *dstAddr, i;

	printf("\n1MB Mem to Mem data transfer Using Memcpy\n");	

	/*
	rBANKCFG |= (1<<6);
	rBANKCON1 |= (1<<7) | (1<<6) | (1<<4);
	*/
	
	srcAddr = (U32 *)(_NONCACHE_STARTADDRESS);
	dstAddr = (U32 *)(_NONCACHE_STARTADDRESS+0x200000);

	for (i=0; i<(0x100000) ;i+=4)
	*srcAddr++ = 0x22222222;
	
	rGPFDAT |= (0x1<<0);
	Delay(1);
	rGPFDAT &= ~(0x1<<0);	
	//DMC4burstmemcpy(0x31000000, 0x31200000, 0x100000);
	DMC8burstmemcpy(0x31000000, 0x31200000, 0x100000);

	rGPFDAT |= (0x1<<0);	
}

void mem_write_word(int address, int end_addr, int pattern)
{
    int i;
    volatile U32 memSum0=0, memSum1=0;    
       
    for(i=address;i<end_addr;i+=4)
    {
        if (!PATTERNADDR)
        {
            memSum0+=*((U32 *)i)=pattern;
            //printf("Address= 0x%08x,    Write= 0x%08x\n",i,*((U32 *)i));
            
            if (PATTERN_INVERT)
            {
                i+=4;
                memSum0+=*((U32 *)i)= ~pattern;            
               // printf("Address= 0x%08x,    Write= 0x%08x\n",i,*((U32 *)i));             
            }
        }
        else            
        {
            memSum0+=*((U32 *)i)=i; 
            //printf("Address= 0x%08x,    Write= 0x%08x\n",i,i);                   
        }
    }
   }

void __irq DmaDone_DMC(void)
{
	//printf("d");
	rSUBSRCPND = BIT_SUB_DMA5|BIT_SUB_DMA0;
	ClearPending(BIT_DMA);
	dma_done_DMC = 1;
}

void Test_MEM_ReadWrite_SMC(void)
{
	int i;

	printf("\n[SROM Controller Memory Write/Read/Compare Test]\n");

	rSMBCR0 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR1 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR2 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR3 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR4 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR5 |= (0x1<<4)|(0x1); // Byte Enable
	
	if (!PATTERNADDR)
	{
	    
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xffff5555);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0x5555ffff);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xffffaaaa);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0x0000ffff);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xffff0000);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xa5a5a5a5);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0x5a5a5a5a);
	}
	else
	{
		mem_write_read_word (START_ADDRESS, END_ADDRESS, 0x00000000);        
	}

	printf("Memory Test Completed.\n");
}

/*
void Test_MEM_Write_SMC_Timingmeasure(void)
{
	int i;

	printf("\n[SROM Controller Memory Write/Read/Compare Test]\n");

	rSMBCR0 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR1 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR2 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR3 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR4 |= (0x1<<4)|(0x1); // Byte Enable
	rSMBCR5 |= (0x1<<4)|(0x1); // Byte Enable
	
	if (!PATTERNADDR)
	{
	    
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xffff5555);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0x5555ffff);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xffffaaaa);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0x0000ffff);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xffff0000);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0xa5a5a5a5);
		mem_write_read_word (START_ADDRESS_SRAM, END_ADDRESS_SRAM, 0x5a5a5a5a);
	}
	else
	{
		mem_write_read_word (START_ADDRESS, END_ADDRESS, 0x00000000);        
	}

	printf("Memory Test Completed.\n");
}
*/
void Test_MEM_Read(void)
{
	int  address, end_addr;
	int i;

	address = 0x0;
	end_addr = 0x1000;
	
	for(i=address;i<end_addr;i+=4)
	{
		printf("Address: 0x%08x,  Read= 0x%08x\n",i,*((U32 *)i));       	        
	}
}
 

///////////////////////////////////////////////////////////////////////////////////
////////////////////                    DMC Main Test                  ///////////////////////////// 
///////////////////////////////////////////////////////////////////////////////////

void * dmc_menu[][2]=
{	
	//(void *)MemoryReadWriteTest,       "SDR R/W Test",
	(void *)Test_MEM_ReadWrite_word,		"SDR Pattern R/W Test by Word",
	(void *)Test_MEM_ReadWrite_Hword,		"SDR Pattern R/W Test by Half Word",
	(void *)Test_MEM_ReadWrite_byte,		"SDR Pattern R/W Test by Byte",
	(void *)Test_AboveAll,					"SDR Pattern R/W Test Above All",
	(void *)Test_MEM_ReadWrite_word_DMCSMC_Complex, "DMC & SMC complex Test",
	(void *)SDR_ModeTest,					"SDR Mode Test",	
	(void *)SDR_ModeTest_WBUF,				"SDR Write Buffer Test",
	(void *)SDR_ModeTest_BSTOP,				"SDR BSTOP Test",
	(void *)SDR_ModeTest_tARFC,				"SDR tARFC timing Test",
	(void *)SDR_ModeTest_tRP,				"SDR tRP timing Test",
	(void *)SDR_PerformanceTest_DMA,		"SDR Performance Test using DMA",
	(void *)SDR_PerformanceTest_ForLoop,	"SDR Performance Test using For Loop",
	(void *)SDR_PerformanceTest_Memcpy,	"SDR Performance Test using Memcpy",
	(void *)Test_MEM_ReadWrite_SMC,			"SROM Controller Read/Write Test      ",
	(void *)Test_MEM_Read,					"Memory Read Test      ",
	0,0
};

void Test_DMC(void)
{  
	int i;

	printf("\nrBANKCFG = %x\n",rBANKCFG);

	rGPFCON = (rGPFCON & ~(0x3<<0))|(0x1<<0);
	rGPFDAT |= (0x1<<0);

	while(1)
	{
		i=0;
		printf("\n\n");
		while(1)
		{   //display menu
   		printf("%2d:%s",i,dmc_menu[i][1]);
	    	i++;
	    	if((int)(dmc_menu[i][0])==0)
	    	{
				printf("\n");
				break;
	    	}
	    	if((i%1)==0)
	    	printf("\n");
		}

		printf("\nSelect (\"-1\" to exit) : ");
		i = GetIntNum();
		if(i==-1) 
	   		break;		// return.
		if( (i<((sizeof(dmc_menu)-1)/8)) )	// select and execute...
	    	( (void (*)(void)) (dmc_menu[i][0]) )();
	}
	
}