hs0_mmc.c

samsung 最新芯片2450 的测试程序.

	}
	else
	{
		SetTransferModeReg_CH0(1, 0, 1, 1, 1);
		SetCommandReg_CH0(25, 0); // CMD25: Multi-Write
	}
	
	if (!WaitForCommandComplete_CH0())
	{
		printf("\nCommand is NOT completed\n");
	}
	ClearCommandCompleteStatus_CH0();		
	
	while(!HS_ADMA_END_ch0);
	while(!HS_DESCRIPTOR_INT_ch0);

	if(!WaitForTransferComplete_CH0())
		{
		printf(("Transfer is NOT Complete\n"));
		}
	ClearTransferCompleteStatus_CH0();
	
	//rHM1_NORINTSTS |= (1<<3);
	
	printf(("\nDMA Write End\n"));
	printf("Press Any key for Data compare\n");

	HS_ADMA_END_ch0=0;
	HS_DESCRIPTOR_INT_ch0=0;	

	Uart_getc();
	/*
	DataRead_ForCompare_CH1(StartAddr);	
	DataCompare_HSMMC_CH1(uSrcAddr, uDstAddr, BlockNum_HSMMC_ch1 * 128);
	*/	
	pISR_SDI_0=(unsigned)HS_ADMA_INT_CH0;
	rINTMSK &= ~(BIT_SDI0);
	rHM0_NORINTSTSEN = (rHM1_NORINTSTSEN & ~(0xffff)) |
						BUFFER_READREADY_STS_INT_EN_CH0| 
						DMA_STS_INT_EN_CH0 |
						TRANSFERCOMPLETE_STS_INT_EN_CH0|
						COMMANDCOMPLETE_STS_INT_EN_CH0;
	rHM0_NORINTSIGEN = (rHM0_NORINTSIGEN & ~(0xffff)) | DMA_SIG_INT_EN_CH0 | TRANSFERCOMPLETE_SIG_INT_EN_CH0;
	
	//SetSystemAddressReg_CH1(SDI_Rx_buffer_HSMMC_CH0);// AHB System Address For Write

	SetADMASystemAddressReg_CH0((U32*)&RdDscrpt[0]);
	SetBlockSizeReg_CH0(7, 512); // Maximum DMA Buffer Size, Block Size				
	SetBlockCountReg_CH0(BlockNum_HSMMC_ch0); // Block Numbers to Write	
	SetArgumentReg_CH0(StartAddr);// Card Start Block Address to Write

	if (BlockNum_HSMMC_ch0 == 1)
	{
		SetTransferModeReg_CH0(0, 1, 0, 1, 1);
		SetCommandReg_CH0(17, 0); // CMD17: Single-Read
	}
	else
	{
		SetTransferModeReg_CH0(1, 1, 1, 1, 1);
		SetCommandReg_CH0(18, 0); // CMD18: Multi-Read
	}

	if (!WaitForCommandComplete_CH0())
	{
		printf(("Command NOT Complete\n"));
	}
	else
		ClearCommandCompleteStatus_CH0();		
		
	while(!HS_ADMA_END_ch0);
	//while(!HS_DESCRIPTOR_INT_ch0);	

	printf(("\nDMA Read End\n"));

	DataCompare_HSMMC_CH0(uSrcAddr, uDstAddr, BlockNum_HSMMC_ch0 * 128);

	HS_ADMA_END_ch0=0;
	HS_DESCRIPTOR_INT_ch0=0;	
	BlockNum_HSMMC_ch0=0;
	
}

void HS_MMC_ADMA_WriteTest_CH0(void)
{

	U32 uSrcAddr;
	U32 uDataSize;
	U32 uNumOfBlocks;
	U32 uSrcAddr1, uSrcAddr2, uSrcAddr3;
	U32 StartAddr;
	U32 i,j;

	U32 uTxBufAddr = SDI_Tx_buffer_HSMMC_CH0;
	U32 uCompareBufAddr = SDI_Compare_buffer_HSMMC_CH0;

	ADMA_DESC_CH0 WrDscrpt[4];

	printf("\nInput Write Start block number : ");
	StartAddr = GetIntNum();
	
	printf("Input number of Block [1~65535] : ");
	BlockNum_HSMMC_ch0 = GetIntNum();

	uDataSize = BlockNum_HSMMC_ch0*512;

	uSrcAddr = SDI_Tx_buffer_HSMMC_CH0;
	uSrcAddr1 = uSrcAddr + uDataSize;
	uSrcAddr2 = uSrcAddr1 + uDataSize;
	uSrcAddr3 = uSrcAddr2 + uDataSize;

	printf("\nSrcAddr = 0x%x",uSrcAddr);
	printf("\nSrcAddr1 = 0x%x",uSrcAddr1);
	printf("\nSrcAddr2 = 0x%x",uSrcAddr2);
	printf("\nSrcAddr3 = 0x%x",uSrcAddr3);

	printf("\n&WrDscrpt[0] = 0x%x",&WrDscrpt[0]);
	printf("\n&WrDscrpt[1] = 0x%x",&WrDscrpt[1]);
	printf("\n&WrDscrpt[2] = 0x%x",&WrDscrpt[2]);
	printf("\n&WrDscrpt[3] = 0x%x",&WrDscrpt[3]);
	
	if(SectorMode_ch0 == 1)
	{
	StartAddr = StartAddr;
	printf("\nSector Mode Addressing");
	}
	else
	{
	StartAddr = StartAddr * 512;
	printf("\nByte Mode Addressing");
	}

	// 1. Make a descriptor table

	GenerateDescriptor_CH0(&WrDscrpt[0], uSrcAddr, uDataSize, ADMA_CONTINUE_CH0, ADMA_INTDis_CH0);
	GenerateDescriptor_CH0(&WrDscrpt[1], uSrcAddr1, uDataSize, ADMA_CONTINUE_CH0, ADMA_INTDis_CH0);
	GenerateDescriptor_CH0(&WrDscrpt[2], uSrcAddr2, uDataSize, ADMA_CONTINUE_CH0, ADMA_INTDis_CH0);
	GenerateDescriptor_CH0(&WrDscrpt[3], uSrcAddr3, uDataSize, ADMA_END_CH0, ADMA_INTEn_CH0);
	
	// 2. Make source data and initialize destination
	
	for ( i=0; i<BlockNum_HSMMC_ch0*128; i++ )
	{
		((U32 *)uSrcAddr)[i] = rand();
		((U32 *)uSrcAddr1)[i] =rand();
		((U32 *)uSrcAddr2)[i] =rand();
		((U32 *)uSrcAddr3)[i] =rand();
	}

	// 5. Writing ADMA mode

	pISR_SDI_0 = (unsigned)HS_ADMA_INT_CH0;
	
	rINTMSK &= ~(BIT_SDI0);				
	rHM0_NORINTSTSEN = (rHM0_NORINTSTSEN & ~(0xffff)) |
						DMA_STS_INT_EN_CH0 |
						TRANSFERCOMPLETE_STS_INT_EN_CH0 |
						COMMANDCOMPLETE_STS_INT_EN_CH0;
	rHM0_NORINTSIGEN = (rHM0_NORINTSIGEN & ~(0xffff)) | DMA_SIG_INT_EN_CH0 | TRANSFERCOMPLETE_SIG_INT_EN_CH0;
	
	SetADMASystemAddressReg_CH0((U32*)&WrDscrpt[0]);
	
	SetBlockSizeReg_CH0(7, 512); // Maximum DMA Buffer Size, Block Size				
	SetBlockCountReg_CH0(BlockNum_HSMMC_ch0*4); // Block Numbers to Write	
	SetArgumentReg_CH0(StartAddr);// Card Start Block Address to Write				
	
	if (uNumOfBlocks == 1)
	{
		SetTransferModeReg_CH0(0, 0, 1, 1, 1);
		SetCommandReg_CH0(24, 0); // CMD24: Single-Write
	}
	else
	{
		SetTransferModeReg_CH0(1, 0, 1, 1, 1);
		SetCommandReg_CH0(25, 0); // CMD25: Multi-Write
	}
	
	if (!WaitForCommandComplete_CH0())
	{
		printf("\nCommand is NOT completed\n");
	}
	ClearCommandCompleteStatus_CH0();		
	
	while(!HS_ADMA_END_ch0);
	//while(!HS_DESCRIPTOR_INT_ch1);

	if(!WaitForTransferComplete_CH0())
		{
		printf(("Transfer is NOT Complete\n"));
		}
	ClearTransferCompleteStatus_CH0();
	
	//rHM0_NORINTSTS |= (1<<3);

	printf("\nDMA interrupt cnt = %x",HS_DESCRIPTOR_INT_ch0);
	printf("\nTransfer Done interrupt cnt = %x",HS_ADMA_END_ch0);
	printf(("\nDMA Write End\n"));

	printf("\nPress Any key for Data compare\n");
	Uart_getc();
	
	DataRead_ForCompare_ADMA_CH0(StartAddr);	
	DataCompare_HSMMC_CH0(uTxBufAddr, uCompareBufAddr, (BlockNum_HSMMC_ch0 * 128)*4);
	
	BlockNum_HSMMC_ch0 = 0;
	wt_cnt_HSMMC_ch0 = 0;
	WriteBlockCnt_INT_ch0 = 0;
	HS_DMA_END_ch0 = 0;
	BufferBoundary_INT_Cnt_ch0 = 0;

	CompareCnt_INT_ch0 = 0;
	Compare_buffer_HSMMC_ch0 = 0;
	HS_ADMA_END_ch0=0;
	HS_DESCRIPTOR_INT_ch0=0;	
	
}


void HS_MMC_ADMA_ReadTest_CH0(void)
{

	U32 uSrcAddr;
	U32 uDataSize;
	U32 uNumOfBlocks;
	U32 uSrcAddr1;
	U32 uDstAddr;
	U32 uDstAddr1,uDstAddr2,uDstAddr3;
	U32 StartAddr;
	U32 i,j,Addr_temp=0;

	U32 uTxBufAddr = SDI_Tx_buffer_HSMMC_CH0;
	U32 uCompareBufAddr = SDI_Compare_buffer_HSMMC_CH0;

	ADMA_DESC_CH0 RdDscrpt[4];

	printf("\nInput Read Start block number : ");
	StartAddr = GetIntNum();
	
	printf("Input number of Block [1~65535] : ");
	BlockNum_HSMMC_ch0 = GetIntNum();

	uDataSize = BlockNum_HSMMC_ch0*512;

	uDstAddr = SDI_Rx_buffer_HSMMC_CH0;
	uDstAddr1 = uDstAddr + uDataSize;
	uDstAddr2 = uDstAddr1 + uDataSize;
	uDstAddr3 = uDstAddr2 + uDataSize;
/*
	printf("\uDstAddr = 0x%x",uDstAddr);
	printf("\uDstAddr1 = 0x%x",uDstAddr1);
	printf("\uDstAddr2 = 0x%x",uDstAddr2);
	printf("\uDstAddr3 = 0x%x",uDstAddr3);
*/	
	if(SectorMode_ch0 == 1)
	{
	StartAddr = StartAddr;
	printf("\nSector Mode Addressing");
	}
	else
	{
	StartAddr = StartAddr * 512;
	printf("\nByte Mode Addressing");
	}

	// 1. Make a descriptor table

	GenerateDescriptor_CH0(&RdDscrpt[0], uDstAddr, uDataSize, ADMA_CONTINUE_CH0, ADMA_INTDis_CH0);
	GenerateDescriptor_CH0(&RdDscrpt[1], uDstAddr1, uDataSize, ADMA_CONTINUE_CH0, ADMA_INTEn_CH0);
	GenerateDescriptor_CH0(&RdDscrpt[2], uDstAddr2, uDataSize, ADMA_CONTINUE_CH0, ADMA_INTDis_CH0);
	GenerateDescriptor_CH0(&RdDscrpt[3], uDstAddr3, uDataSize, ADMA_END_CH0, ADMA_INTEn_CH0);

	// 2. Make source data and initialize destination
	
	for ( i=0; i<BlockNum_HSMMC_ch0*128; i++ )
	{
		((U32 *)uDstAddr)[i] = 0;
		((U32 *)uDstAddr1)[i] = 0;
		((U32 *)uDstAddr2)[i] = 0;
		((U32 *)uDstAddr3)[i] = 0;
	}

	/*
	DataRead_ForCompare_CH0(StartAddr);	
	DataCompare_HSMMC_CH0(uSrcAddr, uDstAddr, BlockNum_HSMMC_ch0 * 128);
	*/	
	#if 0
	pISR_SDI_0=(unsigned)HS_ADMA_INT_CH0;
	rINTMSK &= ~(BIT_SDI0);
	rHM0_NORINTSTSEN = (rHM0_NORINTSTSEN & ~(0xffff)) |
						BUFFER_READREADY_STS_INT_EN_CH0 | 
						DMA_STS_INT_EN_CH0 |
						TRANSFERCOMPLETE_STS_INT_EN_CH0 |
						COMMANDCOMPLETE_STS_INT_EN_CH0;
	rHM0_NORINTSIGEN = (rHM0_NORINTSIGEN & ~(0xffff)) | DMA_SIG_INT_EN_CH0 | TRANSFERCOMPLETE_SIG_INT_EN_CH0;
	#else
	pISR_SDI_0=(unsigned)HS_ADMA_INT_CH0;
	rINTMSK &= ~(BIT_SDI0);				
	rHM0_NORINTSTSEN = (rHM0_NORINTSTSEN & ~(0xffff)) |
						DMA_STS_INT_EN_CH0 |
						TRANSFERCOMPLETE_STS_INT_EN_CH0 |
						COMMANDCOMPLETE_STS_INT_EN_CH0;
	rHM0_NORINTSIGEN = (rHM0_NORINTSIGEN & ~(0xffff)) | DMA_SIG_INT_EN_CH0 | TRANSFERCOMPLETE_SIG_INT_EN_CH0;
	#endif
	//SetSystemAddressReg_CH0(SDI_Rx_buffer_HSMMC_CH0);// AHB System Address For Write

	SetADMASystemAddressReg_CH0((U32*)&RdDscrpt[0]);
	SetBlockSizeReg_CH0(7, 512); // Maximum DMA Buffer Size, Block Size				
	SetBlockCountReg_CH0(BlockNum_HSMMC_ch0*4); // Block Numbers to Read	
	SetArgumentReg_CH0(StartAddr);// Card Start Block Address to read

	if (BlockNum_HSMMC_ch0 == 1)
	{
		SetTransferModeReg_CH0(0, 1, 0, 1, 1);
		SetCommandReg_CH0(17, 0); // CMD17: Single-Read
	}
	else
	{
		SetTransferModeReg_CH0(1, 1, 1, 1, 1);
		SetCommandReg_CH0(18, 0); // CMD18: Multi-Read
	}

	if (!WaitForCommandComplete_CH0())
	{
		printf(("Command NOT Complete\n"));
	}
	else
		ClearCommandCompleteStatus_CH0();		
		
	while(!HS_ADMA_END_ch0);
	//while(!HS_DESCRIPTOR_INT_ch1);	

	printf("\nDMA Read interrupt cnt = %x",HS_DESCRIPTOR_INT_ch0);
	printf("\nTransfer Done interrupt cnt = %x",HS_ADMA_END_ch0);

	Rx_buffer_HSMMC_ch0 = (U32 *)SDI_Rx_buffer_HSMMC_CH0;
	for(j=0 ; j<((512*BlockNum_HSMMC_ch0)/4)*4 ; j++)
	   	{
		      	if(j%4 == 0)
		   		printf("\n0x%04xh : ",Addr_temp);
		       	printf("0x%08x ",*Rx_buffer_HSMMC_ch0++);
		       	Addr_temp += 4;
		}

	HS_ADMA_END_ch0=0;
	HS_DESCRIPTOR_INT_ch0=0;	
	BlockNum_HSMMC_ch0=0;
	
}

void CE_ATA_WriteTest_CH0(void)
{
	U32 Offset;
	U32 i,j,k;
	U32 Arg;
	U32 uSfr;
	U32 ATA_Task[16],  ATA_Task1[16];

	rHM1_NORINTSTS = 0xff;
	ClearPending(BIT_SDI0);
	rINTMSK |= (BIT_SDI0);
	rHM0_NORINTSIGEN &= ~(0xffff);

	rHM0_TRNMOD = rHM0_TRNMOD & ~(0x3<<8);

	CE_ATAInit_CH0();

	//rHM1_TRNMOD = rHM1_TRNMOD & ~(0xffff);
	rHM0_TRNMOD = 0x0;
	printf("\nrHM1_TRNMOD Moon= %x\n",rHM0_TRNMOD);
		

	printf("Input Write Data Offset : ");
	Offset = GetIntNum();

	Tx_buffer_HSMMC_ch0= (U32 *)SDI_Tx_buffer_HSMMC_CH0;
    	for(i=0 ; i<(512*20)/4 ; i++)
    		{
    		*(Tx_buffer_HSMMC_ch0+i) =( i+Offset);
    		//*(Tx_buffer_HSMMC_ch0+i) =0xaaaa5555;
   		}

	pISR_SDI_0=(unsigned)CCS_INT_CH0;
	rINTMSK &= ~(BIT_SDI0);
	rHM0_NORINTSTSEN |= (1<<9);
	rHM0_NORINTSIGEN = rHM0_NORINTSIGEN & ~(0xffff) | (1<<9);	

	rHM0_CONTROL2 |= (1<<11);

	printf("\n------------------Write Start------------------");
	
	SetTransferModeReg_CH0(0, 0, 0, 0, 0);	
	rHM0_BLKSIZE = 0x10;	
	rHM0_ARGUMENT = (0x1<<31) | (0<<16) | (0x10) ;
	rHM0_CMDREG = (60<<8)|(1<<5)|(1<<4)|(1<<3)|(3<<0);

	if (!WaitForCommandComplete_CH0())
	{
		printf(("Command NOT Complete\n"));
	}
	else
		ClearCommandCompleteStatus_CH0();


	while (!(rHM0_NORINTSTS&0x10));
	printf("\nWrite buffer ready\n");

	rHM0_BDATA = (WR_LBA_Low_exp_CH0<< 24) | (WR_Sector_Count_exp_CH0<<16) |(WR_Feature_exp_CH0<<8) |WR_Reserved_CH0 ;	
	rHM0_BDATA = (WR_Reserved_CH0<< 24) | (WR_Control_CH0<<16) |(WR_LBA_High_exp_CH0<<8) |WR_LBA_Mid_exp_CH0 ;	
	rHM0_BDATA = (WR_LBA_Low_CH0<< 24) | (WR_Sector_Count_CH0<<16) |(WR_Feature_CH0<<8) |WR_Reserved_CH0 ;	
	rHM0_BDATA = (WR_Command_CH0<< 24) | (WR_Dev_Head_CH0<<16) |(WR_LBA_High_CH0<<8) |WR_LBA_Mid_CH0 ;	

	if(!WaitForTransferComplete_CH0())
	{
	printf(("Transfer is NOT Complete\n"));
	}
	ClearTransferCompleteStatus_CH0();

	printf("\nATA TASK FILE Write Sequence Finished\n");

	//while (!IsCardInProgrammingState());

#if CEATA_DMA_ch0
	CCS_END_ch0= 0;
	HS_DMA_END_ch0= 0;
	CEATA_ISR_ch0= 0;
/*
	pISR_SDI_1 = (unsigned)HS_DMA_INT;				
	rINTMSK &= ~(BIT_SDI1);				
	rHM_NORINTSTSEN = (rHM_NORINTSTSEN & ~(0xffff)) |
						BUFFER_READREADY_STS_INT_EN | 
						BUFFER_WRITEREADY_STS_INT_EN |
						TRANSFERCOMPLETE_STS_INT_EN |
						COMMANDCOMPLETE_STS_INT_EN;
	rHM_NORINTSIGEN = (rHM_NORINTSIGEN & ~(0xffff)) | TRANSFERCOMPLETE_SIG_INT_EN | (1<<9);	
*/
	pISR_SDI_0=(unsigned)HS_DMA_INT_CH0;
	rHM0_NORINTSTSEN &= ~(DMA_STS_INT_EN_CH0|BLOCKGAP_EVENT_STS_INT_EN_CH0);
	rHM0_NORINTSTSEN |= (1<<9);
	rHM0_NORINTSIGEN = rHM0_NORINTSIGEN & ~(0xffff) | TRANSFERCOMPLETE_SIG_INT_EN_CH0 | (1<<9);
	rINTMSK &= ~(BIT_SDI0);

	SetSystemAddressReg_CH0(SDI_Tx_buffer_HSMMC_CH0);// AHB System Address For Write
	SetTransferModeReg_CH0(1, 0, 0, 1, 1);
	SetBlockSizeReg_CH0(7, 512); // Maximum DMA Buffer Size, Block Size	
	rHM0_TRNMOD = (rHM0_TRNMOD & ~(0x3<<8)) | (1<<8);
	rHM0_BLKCNT = 0x10;
	rHM0_ARGUMENT = (0x1<<31) |(0x10) ;
	rHM0_CMDREG = (61<<8)|(1<<5)|(1<<4)|(1<<3)|(3<<0);

	if (!WaitForCommandComplete_CH0())
	{
		printf("\nCommand is NOT completed\n");
	}
	ClearCommandCompleteStatus_CH0();		
	
	while(!HS_DMA_END_ch0);
	while(!CCS_END_ch0);

	printf("\nDMA Write End");
	printf("\nHS_DMA_END = %x",HS_DMA_END_ch0);
	printf("\nCCS_END = %x",CCS_END_ch0);
	
	rHM0_NORINTSTS |= (1<<3);

	CCS_END_ch0= 0;
	HS_DMA_END_ch0= 0;
	CEATA_ISR_ch0= 0;

#else

	SetTransferModeReg_CH0(1, 0, 0, 1, 0);	
	rHM0_TRNMOD = (rHM0_TRNMOD & ~(0x3<<8)) | (1<<8);
	rHM0_BLKSIZE = 0x200;
	rHM0_BLKCNT = 0x10;
	rHM0_ARGUMENT = (0x1<<31) |(0x10) ;
	rHM0_CMDREG = (61<<8)|(1<<5)|(1<<4)|(1<<3)|(3<<0);
	
	printf("\nrwrite rHM0_TRNMOD = %x\n",rHM0_TRNMOD);
	printf("\nrwrite rHM0_PRNSTS 0 = %x\n",rHM0_PRNSTS);

	if (!WaitForCommandComplete_CH0())
	{
		printf(("Command NOT Complete\n"));
	}
	else
		ClearCommandCompleteStatus_CH0();

	//Uart_getc();
	//Delay(10000);

	for(j=0; j<16; j++)
		{
			if (!WaitForBufferWriteReady_CH0())
				printf("WriteBuffer NOT Ready\n");
			else
				ClearBufferWriteReadyStatus_CH0();

			for(i=0; i<128; i++) //128 = 512/4			
				{
					rHM0_BDATA = *Tx_buffer_HSMMC_ch0++;	
					//Delay(10);
				}
		}

	printf("\nrwrite rHM0_PRNSTS 1= %x\n",rHM0_PRNSTS);

	if(!WaitForTransferComplete_CH0())
		{
		printf(("Transfer is NOT Complete\n"));
		}
	ClearTransferCompleteStatus_CH0();



	printf("\nrwrite rHM0_PRNSTS 2= %x\n",rHM0_PRNSTS);
	printf("\nPolling Write End");
	

#endif


#if 1
	Arg=(1<<16)|(0<<15)|(0xf<<8)|(0x0<<0);
	while(!IssueCommand_CH0(39, Arg, 0));

	printf("\n Write rHM0_RSPREG0 = %x",rHM0_RSPREG0);
		
	printf(("\nData Write End\n"));
	
	//rHM_NORINTSTS |= (1<<9);
	//rHM_ERRINTSTS |=(1<<5);