hs0_mmc.h

samsung 最新芯片2450 的测试程序.

#ifndef __HS0_MMC_H__
#define __HS0_MMC_H__

#ifdef __cplusplus
extern "C" {
#endif


//////////////////////////////////////////////////////////////////////////////////////////////////


void Test_HS_MMC_CH0(void);
void HS_MMC_Reset_CH0(void);
void HS_MMC_ReadTest_CH0(void);
void HS_MMC_WriteTest_CH0(void);
void HS_MMC_EraseBlock_CH0(void);
void HS_MMC_CardDetect_CH0(void);

void HS_MMC_Reset_CH0(void);
void HS_MMC_SETGPIO_CH0(void);
int HS_MMC_init_CH0(void);

void GetResponseData_CH0(U32 uCmd);
void ClockOnOff_CH0(int OnOff);
void ClockConfig_CH0(U32 Clksrc, U32 Divisior);

int WaitForCommandComplete_CH0(void);
int WaitForTransferComplete_CH0(void);
int WaitForBufferWriteReady_CH0(void);

void ClearBufferWriteReadyStatus_CH0(void);
void ClearBufferReadReadyStatus_CH0(void);
void ClearCommandCompleteStatus_CH0(void);
void ClearTransferCompleteStatus_CH0(void);
void ClearErrInterruptStatus_CH0(void);

void SetTransferModeReg_CH0(U32 MultiBlk,U32 DataDirection, U32 AutoCmd12En,U32 BlockCntEn,U32 DmaEn);
void SetArgumentReg_CH0(U32 uArg);
void SetBlockCountReg_CH0(U16 uBlkCnt);
void SetSystemAddressReg_CH0(U32 SysAddr);
void SetBlockSizeReg_CH0(U16 uDmaBufBoundary, U16 uBlkSize);
void SetMMCSpeedMode_CH0(U32 eSDSpeedMode);
void SetSDSpeedMode_CH0(U32 eSDSpeedMode);
void SetCommandReg_CH0(U16 uCmd,U32 uIsAcmd);
void SetClock_CH0(U32 ClkSrc, U16 Divisor);
void SetSdhcCardIntEnable_CH0(U8 ucTemp);
int SetDataTransferWidth_CH0(void);
int SetSDOCR_CH0(void);
int IsCardInProgrammingState_CH0(void);
int IssueCommand_CH0( U16 uCmd, U32 uArg, U32 uIsAcmd);

void InterruptEnable_CH0(U16 NormalIntEn, U16 ErrorIntEn);
int WaitForBufferReadReady_CH0(void);

int SetMMCOCR_CH0(void);

void HostCtrlSpeedMode_CH0(U8 SpeedMode);

void __irq HS_WRITE_INT_CH0(void);
void __irq HS_READ_INT_CH0(void);
void __irq HS_DMA_INT_CH0(void);
void __irq HS_CARD_DETECT_INT_CH0(void);
void HS_MMC_Irq_CH0(void);

void DisplayCardInformation_CH0(void);
void CalculationBPS_HSMMC_CH0(int Time);

void DataCompare_HSMMC_CH0(U32 a0, U32 a1, U32 bytes);
void DataRead_ForCompare_CH0(int StartAddr);
int ReadExtCSD_CH0(void);

void HS_MMC_Write_AgingTest_CH0(void);
void HS_MMC_ADMA_WriteTest_CH0(void);
void HS_MMC_ADMA_ReadTest_CH0(void);

/////////////////////////////////////////////////////////////////////////////////////////////////

void Test_CE_ATA_CH0(void);
void Test_CEATA_CH0(void);
void CE_ATAInit_CH0(void);
void __irq CCS_INT_CH0(void);
void CE_ATA_ReadTest_CH0(void);
void CE_ATA_WriteTest_CH0(void);
int HS_MMC_init_CEATA_CH0(void);

/////////////////////////////////////////////////////////////////////////////////////////////////


#define	RD_Reserved_CH0			0x0		// 0h
#define	RD_Feature_exp_CH0			0x0		// 1h
#define 	RD_Sector_Count_exp_CH0	0x0		// 2h
#define	RD_LBA_Low_exp_CH0		0x0		// 3h
#define	RD_LBA_Mid_exp_CH0		0x0		// 4h
#define	RD_LBA_High_exp_CH0		0x0		// 5h
#define	RD_Control_CH0				0x0		// 6h
#define	RD_Reserved_CH0			0x0		// 7h
#define	RD_Reserved_CH0			0x0		// 8h
#define	RD_Feature_CH0                       0x0		// 9h
#define	RD_Sector_Count_CH0		0x10	// Ah
#define	RD_LBA_Low_CH0				0x0		// Bh
#define	RD_LBA_Mid_CH0				0x1		// Ch
#define	RD_LBA_High_CH0			0x0		// Dh
#define	RD_Dev_Head_CH0			0x40	// Eh
#define	RD_Command_CH0			0x25	// Fh

#define	WR_Reserved_CH0			0x0		// 0h
#define	WR_Feature_exp_CH0			0x0		// 1h
#define 	WR_Sector_Count_exp_CH0	0x0		// 2h
#define	WR_LBA_Low_exp_CH0		0x0		// 3h
#define	WR_LBA_Mid_exp_CH0		0x0		// 4h
#define	WR_LBA_High_exp_CH0		0x0		// 5h
#define	WR_Control_CH0				0x0		// 6h
#define	WR_Reserved_CH0			0x0		// 7h
#define	WR_Reserved_CH0			0x0		// 8h
#define	WR_Feature_CH0                       0x0		// 9h
#define	WR_Sector_Count_CH0		0x10	// Ah
#define	WR_LBA_Low_CH0			0x0		// Bh
#define	WR_LBA_Mid_CH0		0x1		// Ch
#define	WR_LBA_High_CH0			0x0		// Dh
#define	WR_Dev_Head_CH0			0x40	// Eh
#define	WR_Command_CH0			0x35	// Fh

/////////////////////////////////////////////////////////////////////////////////////////////////
//#define	SDHC_MONITOR		 (*(volatile unsigned *)0x4800004c)	
//#define	SDHC_SLOT_INT_STAT		 (*(volatile unsigned *)0x480000fc)	

/////////////////////////////////////////////////////////////////////////////////////////////////
#define	SD_HCLK_CH0	1
#define	SD_EPLL_CH0		2
#define	SD_EXTCLK_CH0	3

#define	NORMAL_CH0	0
#define	HIGH_CH0	1

//Normal Interrupt Signal Enable
#define	READWAIT_SIG_INT_EN_CH0				(1<<10)
#define	CARD_SIG_INT_EN_CH0					(1<<8)
#define	CARD_REMOVAL_SIG_INT_EN_CH0			(1<<7)
#define	CARD_INSERT_SIG_INT_EN_CH0			(1<<6)
#define	BUFFER_READREADY_SIG_INT_EN_CH0		(1<<5)
#define	BUFFER_WRITEREADY_SIG_INT_EN_CH0	(1<<4)
#define	DMA_SIG_INT_EN_CH0					(1<<3)
#define	BLOCKGAP_EVENT_SIG_INT_EN_CH0		(1<<2)
#define	TRANSFERCOMPLETE_SIG_INT_EN_CH0	(1<<1)
#define	COMMANDCOMPLETE_SIG_INT_EN_CH0		(1<<0)

//Normal Interrupt Status Enable
#define	READWAIT_STS_INT_EN_CH0				(1<<10)
#define	CARD_STS_INT_EN_CH0					(1<<8)
#define	CARD_REMOVAL_STS_INT_EN_CH0			(1<<7)
#define	CARD_INSERT_STS_INT_EN_CH0			(1<<6)
#define	BUFFER_READREADY_STS_INT_EN_CH0		(1<<5)
#define	BUFFER_WRITEREADY_STS_INT_EN_CH0	(1<<4)
#define	DMA_STS_INT_EN_CH0					(1<<3)
#define	BLOCKGAP_EVENT_STS_INT_EN_CH0		(1<<2)
#define	TRANSFERCOMPLETE_STS_INT_EN_CH0		(1<<1)
#define	COMMANDCOMPLETE_STS_INT_EN_CH0		(1<<0)

void HS_MMC_ADMATest_CH0(void);

typedef struct tagADMA_DESC_CH0
{
	unsigned uValid : 1;   // [0]
	unsigned uEnd   : 1;   // [1]
	unsigned uInt   : 1;   // [2]
	unsigned uNull  : 1;   // [3]
	unsigned uAct   : 2;   // [5:4]
	unsigned uRsvd  : 10;  // [15:6]
	U16 uDataSz;           // [31:16]
	U32 uDataAddr;
}ADMA_DESC_CH0;

#define ADMA_NOP_CH0	0
#define ADMA_TRAN_CH0	2
#define ADMA_LINK_CH0	3

#define ADMA_END_CH0		1
#define ADMA_CONTINUE_CH0	0
#define ADMA_INTEn_CH0	1
#define ADMA_INTDis_CH0	0

#ifdef __cplusplus
}
#endif
#endif /*__HS0_MMC_H__*/