pcm_test.c

samsung 最新芯片2450 的测试程序.

		if( g_pcmirqstat[irqcnt1].irqstat2 & IRQ_PENDING )
		{
			printf("irq pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_FULL ) 
		{
			printf("tx full pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );	
			pendingcnt++;
		}
		
		printf("irq stat1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
		printf("irq stat2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
		
		if( pendingcnt ==2 )
		{
			printf("ok\n");	
			return TRUE;
		}
		
	}
		
	//printf("rx fifo 0x%x \n",rPCM_RXFIFO1);
	//PCM_fifostat();	
		
	return FALSE;
}



//verify : interrupt pending - irq_pending 1, txfifo_overflow
//specify how it work :       ISR occur - g_interrupt_cnt should be incresed.
//							  writing any value to clrint, 
//							  pcm_irq_stat 's irq pending should be cleared.
//							  bit relating certain interupt should be cleared
bool PCM_Detail_PCM_IRQ_TXOVERFLOW()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;
	
	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;	
	
	PCM_SetInt(TXFIFO_ERROR_OVERFLOW);
	PCM_EnableInt();
	
	PCM_fifostat();

	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//pause	+ dma disalbe for fifo control

	j = (g_oPCMState.PCMPort==0)? 32-FIFO_TXFIFO_COUNT0 : 32-FIFO_TXFIFO_COUNT1;
	//write until full
	for(i=0 ; i<j; i++)
	{
		*rPCM_TXFIFO = 0x1111;
		PCM_fifostat();
		printf("^--one write\n");
	}
	
	irqcnt1 = g_interrupt_cnt;
	//to make overflow	
	*rPCM_TXFIFO = 0x1111;
	PCM_fifostat();	
	
	//wait for IRQ for secure
	i=0;
	while( g_interrupt_cnt ==0 )
	{
		i++;
		if(i>0xfff) break;
	}		
	irqcnt2 = g_interrupt_cnt;
	
	if(irqcnt2 == (irqcnt1 +1 ) ) 
	{
		int pendingcnt=0;
		//ok. interrupt is occured.
		
		if( g_pcmirqstat[irqcnt1].irqstat1 & IRQ_PENDING ) 
		{
			printf("irq pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_ERROR_OVERFLOW ) 
		{
			printf("tx overflow pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );	
			pendingcnt++;
		}
		
		if( g_pcmirqstat[irqcnt1].irqstat2 & IRQ_PENDING )
		{
			printf("irq pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_ERROR_OVERFLOW ) 
		{
			printf("tx overflow pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );	
			pendingcnt++;
		}
		
		printf("irq stat1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
		printf("irq stat2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
		
		if( pendingcnt ==2 )
		{
			printf("ok\n");	
			return TRUE;
		}
		
	}
		
	//printf("rx fifo 0x%x \n",rPCM_RXFIFO1);
	//PCM_fifostat();	
		
	return FALSE;
}


//verify : interrupt pending - en_irq_to_arm disalbed-> irq_pending 0
//specify how it work :       ISR not occur - g_interrupt_cnt should be incresed.
//							  pcm_irq_stat 's irq pending should be 0
//							  bit relating certaing interupt should be ??
bool PCM_Detail_PCM_IRQ_NOTPENDING_TXFULL()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;

#if 0
	PCM_DisableInt();
	PCM_SetInt(0);//
//	PCM_EnableInt();//interrupt will not be occur.	
#elif 0
	PCM_DisableInt();//interrupt will not be occur.	
//	PCM_SetInt(TXFIFO_FULL|TXFIFO_ALMOST_FULL|TXFIFO_ERROR_OVERFLOW);//->irq pending, full, almost full
//	PCM_SetInt(TXFIFO_FULL);//->irq pending, full, almost full	
//	PCM_SetInt(TXFIFO_ALMOST_FULL);//->irq pending, full, almost full	
//	PCM_SetInt(TXFIFO_ERROR_OVERFLOW);//->full, almost full	
	PCM_SetInt(0);//->full, almost full	
#elif 1
	PCM_DisableInt();//interrupt will not be occur.	
	PCM_SetInt(TXFIFO_FULL|TXFIFO_ERROR_OVERFLOW);
	//PCM_SetInt(TXFIFO_ERROR_OVERFLOW);//once pending
#endif
	
	PCM_fifostat();

	rPCM_CTL1&= ~(PCM_TX_DMA_EN | PCM_PCM_ENABLE);	
	PCM_fifostat();
	
	
	j = 32-FIFO_TXFIFO_COUNT;
	for(i=0;i<j;i++)
	{
		rPCM_TXFIFO1=0x1111;
		PCM_fifostat();	
	}
	
	irqcnt1 = g_interrupt_cnt;
//	g_pcmirqstat[irqcnt1].irqstat1 = rPCM_IRQ_STAT1;

//full(keeping)->overflow(once)
PCM_EnableInt();//interrupt will not be occur.	
//
		
	//to test overflow	
	rPCM_TXFIFO1=0x1111; // at the point of read irq will be occur.	
	PCM_fifostat();

//
for(i=0;i<g_interrupt_cnt;i++)
{
printf("irq pending%d 0x%x\n",i, g_pcmirqstat[i].irqstat1 );	
printf("irq pending%d 0x%x\n",i, g_pcmirqstat[i].irqstat2 );	
}
	
	//wait for IRQ for secure
	i=0;
	while( g_interrupt_cnt ==0 )
	{
		i++;
		if(i>0xfff) break;
	}			
	irqcnt2 = g_interrupt_cnt;
//	g_pcmirqstat[irqcnt1].irqstat2 = rPCM_IRQ_STAT1;	
	
	if(irqcnt2 == irqcnt1  ) 
	{
		int pendingcnt=0;
		//ok. interrupt is not occured.
		
		if( g_pcmirqstat[irqcnt1].irqstat1 & IRQ_PENDING ) 
		{
			printf("irq pending1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_FULL ) 
		{
			printf("tx full pending1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );	
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_ALMOST_FULL ) 
		{
			printf("tx almost full pending1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );	
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_ERROR_OVERFLOW) 
		{
			printf("tx overflow pending1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );	
			pendingcnt++;
		}
		
		if( g_pcmirqstat[irqcnt1].irqstat2 & IRQ_PENDING )
		{
			printf("irq pending2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_FULL ) 
		{
			printf("tx full pending2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );	
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_ALMOST_FULL ) 
		{
			printf("tx almost full pending2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );	
			pendingcnt++;
		}		
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_ERROR_OVERFLOW ) 
		{
			printf("tx overflow pending2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );	
			pendingcnt++;
		}
		
		printf("irq stat1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
		printf("irq stat2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
		
		if( pendingcnt ==0 )
		{
			printf("ok\n");	
			return TRUE;
		}
		
	}
		
	//printf("rx fifo 0x%x \n",rPCM_RXFIFO1);
	//PCM_fifostat();	
		
	return FALSE;
}



//verify : interrupt pending - irq_pending 1, txfifo_almostempty(fifocnt<dipstick=8)
//specify how it work :       ISR occur - g_interrupt_cnt should be incresed.
//							  writing any value to clrint, 
//							  pcm_irq_stat 's irq pending should be cleared.
//							  bit relating certaing interupt should be cleared.
bool PCM_Detail_PCM_IRQ_TXALMOSTEMPTY()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;

	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;
	
	
	PCM_SetInt(TXFIFO_ALMOST_EMPTY);
	PCM_EnableInt();
	
	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//pause	+ dma disalbe for fifo control

	PCM_fifostat();

	//to make almost empty-1
	j = (g_oPCMState.PCMPort==0)? FIFO_TXFIFO_COUNT0-(TXFIFO_DIPSTICK0-1)-1 :
								FIFO_TXFIFO_COUNT1-(TXFIFO_DIPSTICK1-1)-1 ;
	for(i=0;i<j;i++)
	{
		testreg = rPCM_TXFIFO1;
		PCM_fifostat();
		printf("^--one read\n");	
	}
	
	irqcnt1 = g_interrupt_cnt;
	
	//to test almost empty.	
	testreg = rPCM_TXFIFO1; // at the point of read irq will be occur.	
	PCM_fifostat();
	
	//wait for IRQ for secure
	i=0;
	while( g_interrupt_cnt ==0 )
	{
		i++;
		if(i>0xfff) break;
	}		
	irqcnt2 = g_interrupt_cnt;
	
	if(irqcnt2 == (irqcnt1 +1 ) ) 
	{
		int pendingcnt=0;
		//ok. interrupt is occured.
		
		if( g_pcmirqstat[irqcnt1].irqstat1 & IRQ_PENDING ) 
		{
			printf("irq pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_ALMOST_EMPTY ) 
		{
			printf("tx almost empty pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );	
			pendingcnt++;
		}
		
		if( g_pcmirqstat[irqcnt1].irqstat2 & IRQ_PENDING )
		{
			printf("irq pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_ALMOST_EMPTY ) 
		{
			printf("tx almost empty pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );	
			pendingcnt++;
		}
		
		printf("irq stat1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
		printf("irq stat2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
		
		if( pendingcnt ==2 )
		{
			printf("ok\n");	
			return TRUE;
		}
		
	}
		
	return FALSE;
}

//verify : interrupt pending - irq_pending 1, txfifo_empty
//specify how it work :       ISR occur - g_interrupt_cnt should be incresed.
//							  writing any value to clrint, 
//							  pcm_irq_stat 's irq pending should be cleared.
//							  bit relating certaing interupt should be cleared.
bool PCM_Detail_PCM_IRQ_TXEMPTY()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;

	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;
	
	PCM_SetInt(TXFIFO_EMPTY);
	PCM_EnableInt();
	
	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//pause	+ dma disalbe for fifo control
	PCM_fifostat();

	j = (g_oPCMState.PCMPort==0)?FIFO_TXFIFO_COUNT0-1 : FIFO_TXFIFO_COUNT1-1;
	
	for(i=0;i<j;i++)
	{
		testreg = *rPCM_TXFIFO;
		PCM_fifostat();
		printf("^--one read\n");
	}
	
	irqcnt1 = g_interrupt_cnt;
	
	//to test empty.	
	testreg = *rPCM_TXFIFO; // at the point of read irq will be occur.	
	PCM_fifostat();
	
	//wait for IRQ for secure
	i=0;
	while( g_interrupt_cnt ==0 )
	{
		i++;
		if(i>0xfff) break;
	}		
	irqcnt2 = g_interrupt_cnt;
	
	if(irqcnt2 == (irqcnt1 +1 ) ) 
	{
		int pendingcnt=0;
		//ok. interrupt is occured.
		
		if( g_pcmirqstat[irqcnt1].irqstat1 & IRQ_PENDING ) 
		{
			printf("irq pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_EMPTY ) 
		{
			printf("tx empty pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );	
			pendingcnt++;
		}
		
		if( g_pcmirqstat[irqcnt1].irqstat2 & IRQ_PENDING )
		{
			printf("irq pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_EMPTY ) 
		{
			printf("tx empty pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );	
			pendingcnt++;
		}
		
		printf("irq stat1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
		printf("irq stat2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
		
		if( pendingcnt ==2 )
		{
			printf("ok\n");	
			return TRUE;
		}
		
	}
		
	return FALSE;
}



//verify : interrupt pending - irq_pending 1, txfifo_starve
//specify how it work :       ISR occur - g_interrupt_cnt should be incresed.
//							  writing any value to clrint, 
//							  pcm_irq_stat 's irq pending should be cleared.
//							  bit relating certaing interupt should be cleared.
bool PCM_Detail_PCM_IRQ_TXSTARVE()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;

	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;
	
	PCM_SetInt(TXFIFO_ERROR_STARVE);
	PCM_EnableInt();

	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//pause	+ dma disalbe for fifo control	
	PCM_fifostat();


	j = (g_oPCMState.PCMPort==0)? FIFO_TXFIFO_C