meminit.s

samsung 最新芯片2450 的测试程序.

				GET		Option.inc
				GET		2450addr.inc

				EXPORT	InitMEM
				EXPORT	InitSSMC

				AREA	|C$$code|, CODE, READONLY

	IF :DEF: DDR2

InitMEM		PROC

				;Set GPK port when using x32 bus width.
				ldr		r0,=GPKCON
				ldr		r1,=0xaaaaaaaa	; set Sdata[31:16]
				str		r1, [r0]
				
				;Set SDR Memory parameter control registers
 				ldr		r0,=MEMDATA
				ldr		r1,=BANKCFG	;
				add		r2, r0, #12	;End address of MEMDATA
0
				ldr		r3, [r0], #4
				str		r3, [r1], #4
				cmp		r2, r0
				bne		%B0
				
				ldr		r2,=RSTSTAT			;
				ldr		r1,[r2]
				cmp 	r1, #0x1	
				bne		GOM			

				ldr		r2,=BANKCON1			;	4nd	:	Issue a PALL command
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x1<<0)			
				str		r1,[r2]	

				ldr		r2,=BANKCON3			;	5th	:	Issue a EMRS2 command
				ldr		r3,=0xffff0000
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,#(BA_EMRS2<<30)
				str		r1,[r2]	

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x3<<0)			
				str		r1,[r2]

				ldr		r2,=BANKCON3			;	6th	:	Issue a EMRS3 command
				ldr		r3,=0xffff0000
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,#(BA_EMRS3<<30)
				str		r1,[r2]

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x3<<0)			
				str		r1,[r2]

				ldr		r2,=BANKCON3			;	7th	:	Issue a EMRS1 command
				ldr		r3,=0xffff0000
				ldr		r4,=((BA_EMRS1<<30)+(RDQS_DIS<<27)+(nDQS_DIS<<26)+(OCD_MODE_EXIT<<23)+(DLL_EN<<16)) 
				                      ; (0x1<<30)|(0x0<<27)|(0x1<<26)|(0x0<<23)|(0x0<<16)
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,r4
				str		r1,[r2]

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x3<<0)			
				str		r1,[r2]

				ldr		r2,=BANKCON3			;	8th	:	Issue a MRS command
				ldr		r3,=0xffff
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,#((BA_MRS<<14)+(DLL_RESET_HIGH<<8)+(TM<<7)+(CL_MRS<<4))
				str		r1,[r2]
				
				ldr		r2,=BANKCON1				
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x2<<0)			
				str		r1,[r2]

				ldr		r2,=BANKCON1			;	9nd	:	Issue a PALL command
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x1<<0)			
				str		r1,[r2]

				ldr		r4,=REFRESH				;	10th : wait 2 auto - clk
				ldr		r0,=0x20
				str		r0,[r4]					
				
				ldr		r2,=BANKCON3			;	11th	:	Issue a MRS command
				ldr		r3,=0xffff
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,#((BA_MRS<<14)+(DLL_RESET_LOW<<8)+(TM<<7)+(CL_MRS<<4))
				str		r1,[r2]
				
				ldr		r2,=BANKCON1				
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x2<<0)			
				str		r1,[r2]

				mov	r0, #0x100					;	Wait 200 clock
0				subs	r0, r0,#1;
				bne	%B0		
				
				ldr		r2,=BANKCON3			;	12th	:	Issue a EMRS1 command For OCD Mode Set to default
				ldr		r3,=0xffff0000
				ldr		r4,=((BA_EMRS1<<30)+(RDQS_DIS<<27)+(nDQS_DIS<<26)+(OCD_MODE_DEFAULT<<23)+(DLL_EN<<16))
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,r4
				str		r1,[r2]

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x3<<0)			
				str		r1,[r2]

				ldr		r2,=BANKCON3
				ldr		r3,=0xffff0000
				ldr		r4,=((BA_EMRS1<<30)+(RDQS_DIS<<27)+(nDQS_DIS<<26)+(OCD_MODE_EXIT<<23)+(DLL_EN<<16))
				ldr		r1,[r2]
				bic		r1,r1,r3
				orr		r1,r1,r4
				str		r1,[r2]

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x3<<0)			
				str		r1,[r2]
				
				ldr		r4,=REFRESH			;	13fh : refresh  normal
				ldr		r0,=REFCYC
				str		r0,[r4]					

				ldr		r2,=BANKCON1		;	14th	:	Issue a Normal mode
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				str		r1,[r2]
				
GOM				bx		lr
				
				ENDP
				
				LTORG

MEMDATA			DATA
				DCD		((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<1)+(BW<<0))
				DCD		((DQSDelay<<28)+(1<<26)+(BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4))
				DCD		((tRAS<<20)+(tARFC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
				;DCD		((BA_MRS<<14)+(DLL_RESET<<8)+(TM<<7)+(CL_MRS<<4))

	ELIF :DEF: mDDR
				
InitMEM		PROC

				;Set GPK port when using x32 bus width.
				ldr		r0,=GPKCON
				ldr		r1,=0xaaaaaaaa	; set Sdata[31:16]
				str		r1, [r0]
				
				;Set SDR Memory parameter control registers
 				ldr		r0,=MEMDATA
				ldr		r1,=BANKCFG	;
				add		r2, r0, #16	;End address of MEMDATA
0
				ldr		r3, [r0], #4
				str		r3, [r1], #4
				cmp		r2, r0
				bne		%B0

;				ldr		r2,=RSTSTAT			;
;				ldr		r1,[r2]
;				cmp 	r1, #0x1	
;				bne		GOM		

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x1<<0)			;	4nd	:	Issue a PALL command
				str		r1,[r2]			

				ldr		r4,=REFRESH			;	5fh : refresh cycle every 255-clock cycles
				ldr		r0,=0xff
				str		r0,[r4]					
				
				
				
				mov	r0, #0x100					;	6th : wait 2 auto - clk
0				subs	r0, r0,#1;
				bne	%B0	

				bic		r1,r1,#(0x3<<0)			;	7th	:	Issue a MRS command
				orr		r1,r1,#(0x2<<0)
				str		r1,[r2]			

				ldr		r4,=REFRESH			;	8fh : refresh  normal
				ldr		r0,=REFCYC
				str		r0,[r4]					

				orr		r1,r1,#(0x3<<0)			;	9th	:	Issue a EMRS command
				str		r1,[r2]			

				bic		r1,r1,#(0x3<<0)			;	10th	:	Issue a Normal mode
				str		r1,[r2]			

;GOM				bx		lr
				bx		lr
				
				ENDP
				
				LTORG

MEMDATA			DATA
				DCD		((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<1)+(BW<<0))
				DCD		((DQSDelay<<28)+(1<<26)+(BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4))
				DCD		((tRAS<<20)+(tARFC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
				DCD		((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))

	ELIF :DEF: mSDR
				
InitMEM		PROC

				;Set GPK port when using x32 bus width.
				ldr		r0,=GPKCON
				ldr		r1,=0xaaaaaaaa	; set Sdata[31:16]
				str		r1, [r0]
				
				;Set SDR Memory parameter control registers
 				ldr		r0,=MEMDATA
				ldr		r1,=BANKCFG	;
				add		r2, r0, #16	;End address of MEMDATA
0
				ldr		r3, [r0], #4
				str		r3, [r1], #4
				cmp		r2, r0
				bne		%B0

;				ldr		r2,=RSTSTAT			;
;				ldr		r1,[r2]
;				cmp 	r1, #0x1	
;				bne		GOM		

				ldr		r2,=BANKCON1
				ldr		r1,[r2]
				bic		r1,r1,#(0x3<<0)
				orr		r1,r1,#(0x1<<0)			;	4nd	:	Issue a PALL command
				str		r1,[r2]			

				ldr		r4,=REFRESH			;	5fh : refresh cycle every 255-clock cycles
				ldr		r0,=0xff
				str		r0,[r4]					
				
				
				
				mov	r0, #0x100					;	6th : wait 2 auto - clk
0				subs	r0, r0,#1;
				bne	%B0	

				bic		r1,r1,#(0x3<<0)			;	7th	:	Issue a MRS command
				orr		r1,r1,#(0x2<<0)
				str		r1,[r2]			

				ldr		r4,=REFRESH			;	8fh : refresh  normal
				ldr		r0,=REFCYC
				str		r0,[r4]					

				orr		r1,r1,#(0x3<<0)			;	9th	:	Issue a EMRS command
				str		r1,[r2]			

				bic		r1,r1,#(0x3<<0)			;	10th	:	Issue a Normal mode
				str		r1,[r2]			

;GOM				bx		lr
				bx		lr
				
				ENDP
				
				LTORG

MEMDATA			DATA
				DCD		((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<1)+(BW<<0))
				DCD		((DQSDelay<<28)+(1<<26)+(BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4))
				DCD		((tRAS<<20)+(tARFC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
				DCD		((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))

		ENDIF

InitSSMC		PROC

				;Set SSMC Memory parameter control registers : AMD Flash
				ldr		r0,=SMBIDCYR0
				ldr		r1,=IDCY0
				str		r1,[r0]
				
				ldr		r0,=SMBWSTRDR0
				ldr		r1,=WSTRD0
				str		r1,[r0]
				
				ldr		r0,=SMBWSTWRR0
				ldr		r1,=WSTWR0
				str		r1,[r0]
				
				ldr		r0,=SMBWSTOENR0
				ldr		r1,=WSTOEN0
				str		r1,[r0]
				
				ldr		r0,=SMBWSTWENR0
				ldr		r1,=WSTWEN0
				str		r1,[r0]
				
				ldr		r0,=SMBCR0
				ldr		r1,=(SMBCR0_2+SMBCR0_1+SMBCR0_0)
				str		r1,[r0]
				
				ldr		r0,=SMBWSTBRDR0
				ldr		r1,=WSTBRD0
				str		r1,[r0]

				
				ldr		r0,=SMBWSTBRDR0
				ldr		r1,=WSTBRD0
				str		r1,[r0]

				ldr		r0,=SSMCCR
				ldr		r1,=((MemClkRatio<<1)+(SMClockEn<<0))
				str		r1,[r0]
				
				bx		lr
				
				ENDP

				LTORG


				
				END