usbdev.c

samsung 最新芯片2450 的测试程序.

								g_uEp0State = EP0_GET_STATUS4;
							break;

						default:
							break;
					}
					break;

				case STANDARD_GET_INTERFACE:
					g_uEp0State = EP0_INTERFACE_GET;
					break;

				case STANDARD_SET_INTERFACE:
					g_poInterfaceGet->AlternateSetting= g_poDeviceRequest->wValue_L;
					g_uEp0State = EP0_STATE_INIT;
					break;

				case STANDARD_SYNCH_FRAME:
					g_uEp0State = EP0_STATE_INIT;
					break;

				default:
					break;
			}
		}
	}
	TransferEp0();


}


// Not Supporting About Set Descriptor for USB Standard
void StandardSetDescriptor(void)
{
	// CLR_EP0_CSR_OUT_PACKET_READY;
}


// ======================================================================
// TransferEp0()
//
// This is function for Control Transfer Transmit.
// ======================================================================

void TransferEp0(void)
{
	U32 i;
	U32 dataLength;
	U16 usSysStatus;
	
	U32 tmp;
	U32 m,n=0;
	U32 cha;
	

// 	CLR_EP0_CSR_OUT_PACKET_READY;
	switch (g_uEp0State)
	{
		case EP0_STATE_INIT:
			break;

		// === GET_DESCRIPTOR:DEVICE ===
		case EP0_STATE_GD_DEV_0_0:
			#ifdef STALL_CHECK
				Outp32(EP0_CON_REG, 0x2);
			#else 
					
					Outp32(BYTE_WRITE_CNT_REG, DeviceRequestLength&0x3ff);
					WrPktEp0((U8 *)g_poDescDevice+0, DeviceRequestLength&0x3ff); // EP0_PKT_SIZE
					g_uEp0State = EP0_STATE_INIT;
				 
					
			
			#endif
			break;

		case EP0_STATE_GD_CFG_0:
			Outp32(BYTE_WRITE_CNT_REG, 32);
		
			WrPktEp0((U8 *)&g_poDesc->oDescConfig+0, 32); // EP0_PKT_SIZE
		    DeviceRequestLength=0;
			g_uEp0State = EP0_STATE_INIT;
			
		//	DbgUsb(("EndpointZeroTransfer(EP0_STATE_GD_CFG) =%x\n",DeviceRequestLength));
		
			
			break;
		case EP0_STATE_GD_CFG_ONLY_0:
			Outp32(BYTE_WRITE_CNT_REG, 9);
			WrPktEp0((U8 *)&g_poDesc->oDescConfig+0, 9); // EP0_PKT_SIZE
			g_uEp0State = EP0_STATE_INIT;
			break;
		
		// === GET_DESCRIPTOR:CONFIGURATION ONLY===
		
		case EP0_STATE_GD_DEV_QUALIFIER:
		//   DbgUsb(("\n MCU >> Get Device Qualifier Descriptor \n"));
		    Outp32(BYTE_WRITE_CNT_REG, 4);
			WrPktEp0((U8 *)aDeviceQualifierDescriptor+0, 4);
			g_uEp0State = EP0_STATE_INIT;
			break;
			
		case EP0_STATE_GD_DEV_QUALIFIER_1:
		//   DbgUsb(("\n MCU >> Get Device Qualifier Descriptor \n"));
		    
		    Outp32(BYTE_WRITE_CNT_REG, 10);
			WrPktEp0((U8 *)aDeviceQualifierDescriptor+0, 10);
			g_uEp0State = EP0_STATE_INIT;
			break;

        case EP0_STATE_GD_DEV_OTHER_SPEED:
			Set_OtherSpeedConf_DescriptorTable(DeviceRequestLength&0x3ff);
			g_uEp0State = EP0_STATE_INIT;
						
			break;

		// === GET_DESCRIPTOR:ENDPOINT 1 ONLY===
		case EP0_STATE_GD_EP0_ONLY_0:
			Outp32(BYTE_WRITE_CNT_REG, ENDPOINT_DESC_SIZE);
			Inp32(SYS_STATUS_REG, usSysStatus);
			WrPktEp0((U8 *)&g_poDesc->oDescEndpt1+0, ENDPOINT_DESC_SIZE);
			g_uEp0State = EP0_STATE_INIT;
			break;

		// === GET_DESCRIPTOR:ENDPOINT 2 ONLY===
		case EP0_STATE_GD_EP1_ONLY_0:
			Outp32(BYTE_WRITE_CNT_REG, ENDPOINT_DESC_SIZE);
			Inp32(SYS_STATUS_REG, usSysStatus);
			WrPktEp0((U8 *)&g_poDesc->oDescEndpt3+0, ENDPOINT_DESC_SIZE);
			g_uEp0State = EP0_STATE_INIT;
			break;


		case EP0_STATE_GD_STR_I0:
			DbgUsb(("[GDS0_%d]", g_uEp0SubState));
			Outp32(BYTE_WRITE_CNT_REG, 4);
			WrPktEp0(aDescStr0, 4);
			g_uEp0State = EP0_STATE_INIT;
	
			break;

			case EP0_STATE_GD_STR_I1:
			DbgUsb(("[GDS1_%d]", g_uEp0SubState));
			
				Outp32(BYTE_WRITE_CNT_REG, 22);
				WrPktEp0(aDescStr1, 22);
				
				g_uEp0State = EP0_STATE_INIT;
				
			
			break;
			
			case EP0_STATE_GD_STR_I2:
			DbgUsb(("[GDS2_%d]", g_uEp0SubState));
				Outp32(BYTE_WRITE_CNT_REG, 44);
				WrPktEp0(aDescStr2, 44);
				g_uEp0State = EP0_STATE_INIT;
			
		
			break;
		


		case EP0_INTERFACE_GET:
			Outp32(BYTE_WRITE_CNT_REG, 1);
			WrPktEp0((U8 *)g_poInterfaceGet+0, 1);
			g_uEp0State = EP0_STATE_INIT;
			break;


		case EP0_GET_STATUS0:
			Outp32(BYTE_WRITE_CNT_REG, 1);
			WrPktEp0((U8 *)g_poStatusGet+0, 1);
			g_uEp0State = EP0_STATE_INIT;
			break;

		case EP0_GET_STATUS1:
			Outp32(BYTE_WRITE_CNT_REG, 1);
			WrPktEp0((U8 *)g_poStatusGet+1, 1);
			g_uEp0State = EP0_STATE_INIT;
			break;

		case EP0_GET_STATUS2:
			Outp32(BYTE_WRITE_CNT_REG, 1);
			WrPktEp0((U8 *)g_poStatusGet+2, 1);
			g_uEp0State = EP0_STATE_INIT;
			break;

		case EP0_GET_STATUS3:
			Outp32(BYTE_WRITE_CNT_REG, 1);
			WrPktEp0((U8 *)g_poStatusGet+3, 1);
			g_uEp0State = EP0_STATE_INIT;
			break;

		case EP0_GET_STATUS4:
			Outp32(BYTE_WRITE_CNT_REG, 1);
			WrPktEp0((U8 *)g_poStatusGet+4, 1);
			g_uEp0State = EP0_STATE_INIT;
			break;

		default:
			break;


	}
}

// ======================================================================
// HandleBulkIn()
//
// This is function for Endpoint One ( Bulk In)function routine.
// ======================================================================
void HandleEvent_BulkIn(void)
{
	U16 ep1csr;
	U32 temp;

	// EP1 CSR register status check
	Outp32(INDEX_REG, 0x01);
	Inp32(EP_STATUS_REG, ep1csr);
	Outp32(EP_STATUS_REG, ep1csr);
	Inp32(DMA_TOTAL_CNT1_REG, temp);
    
	if (ep1csr & EP_SENT_STALL) { // SENT STALL : protocol stall.
		DbgUsb(("Sent Stall \n"));
		Outp32(EP_STATUS_REG, EP_SENT_STALL);
	}

	if (ep1csr & EP_TX_SUCCESS)
	{
		Outp32(EP_STATUS_REG, EP_TX_SUCCESS); // Endpoint Status Register Clear
		if (g_eOpMode == USB_CPU)
		{
			if (g_uBulkInCount != 0)
				PrepareEp1Fifo(g_uBulkInAddr);
		}
	}

	if (DMA_TOTAL_COUNT_ZERO & ep1csr)
	{
		printf("USB_DMA_MODE, DMA TX Done(DMA_TOTAL_COUNT_ZERO) !!\n");
		Outp32(DMA_CON_REG, DMA_TX_STOP|USB_INT_MODE);
		Outp32(FCON, DMA_DISABLE);
	}
}

// ======================================================================
// HandleBulkOut()
//
// This is function for Endpoint Three ( Bulk Out)function routine.
// ======================================================================
U32 checkTest = 0;

void HandleEvent_BulkOut(void)
{
	U32 ReadData;
	U32 RecDataCnt;
	U16 ep3csr, ep2con, sys_status;
	U32 CBWSignature=0, CBWTag=0, i;
	U8  TempBuf[16];
	U16 fifoCnt;
	U16 fifoCntByte;
	U32 DmaCurrAddr;
	U32 temp;
	U32 uUploadSize;
	U32 uUploadAddr;
	U32 uDownloadFileSize;
	
	U32 j;
	
	Outp32(INDEX_REG, EP3);
	Inp32(EP_STATUS_REG, ep3csr);
	Outp32(EP_STATUS_REG, ep3csr);
 	DbgUsb(("Bulk Out Int, ep3csr : %x\n", ep3csr));
	Inp32(DMA_TOTAL_CNT1_REG, temp);
	DbgUsb(("EP3: DMA_TOTAL_CNT1_REG : %x\n", temp));

	if (ep3csr & EP_SENT_STALL) // SENT STALL : protocol stall.
	{
		Outp32(EP_STATUS_REG, EP_SENT_STALL);
		return;
	}

	if (ep3csr & EP_FIFO_FLUSH)
	{
		Outp32(EP_CON_REG, EP_FIFO_FLUSH);
		return;
	}

	if (DMA_TOTAL_COUNT_ZERO & ep3csr)
	{		
	    checkTest = 1;
		DbgUsb(("USB_DMA_MODE, DMA RX Done(DMA_TOTAL_COUNT_ZERO) !!\n"));
		
		Outp32(DMA_CON_REG, DMA_RX_STOP|USB_INT_MODE);
		
		g_eOpMode = USB_CPU;
		Inp32(DMA_MEg_CURRENT_ADDR, DmaCurrAddr);
		g_pDownPt = (U8 *)DmaCurrAddr;
		
		
		Outp32(FCON, DMA_DISABLE);
		
		DbgUsb(("DMA_TOTAL_COUNT_ZERO, ep3csr : %x\n", ep3csr));

		dma_done =1;
	    
	    if (!ep3csr & EP_RX_SUCCESS)// if interrupt is not genarated then check the RX_success bit.
	  	return;
	  
	}

	if (ep3csr & EP_RX_SUCCESS)
	{
		DbgUsb(("EP3_RX_PKT_SUCCESS\n"));
		if (g_uDownloadFileSize==0)
		{
			Inp32(BYTE_READ_CNT_REG, fifoCnt);

			if (fifoCnt == 5)
			{
				RdPktEp3((U8 *)TempBuf, 10);
				temp = *((U8 *)(TempBuf+8))+
					(*((U8 *)(TempBuf+9))<<8);
				DbgUsb(("temp: %x\n", temp));
				if (temp==0x1)
				{
					uUploadAddr =
						*((U8 *)(TempBuf+0))+
						(*((U8 *)(TempBuf+1))<<8)+
						(*((U8 *)(TempBuf+2))<<16)+
						(*((U8 *)(TempBuf+3))<<24);

					uUploadSize =
						*((U8 *)(TempBuf+4))+
						(*((U8 *)(TempBuf+5))<<8)+
						(*((U8 *)(TempBuf+6))<<16)+
						(*((U8 *)(TempBuf+7))<<24);
				
					printf("UploadAddress : %x, UploadSize: %x\n", uUploadAddr, uUploadSize);
					if (g_eOpMode == USB_CPU)
					{
						DbgUsb(("CPU_MODE Bulk In Function\n"));
					
				
						g_uBulkInCount = uUploadSize;
						PrepareEp1Fifo(uUploadAddr);
					}
					else
					{
						DbgUsb(("DMA_MODE Bulk In Function\n"));
						Outp32(FCON, DMA_ENABLE);				// USB Dma Enable in Core Outside
						Outp32(INDEX_REG, EP1);					// IN Direction  Device -> Host
						Outp32(DMA_IF_CON_REG, MAX_BURST_INCR16);
						Outp32(BYTE_WRITE_CNT_REG, g_uEp1MaxPktSize);
						Outp32(MAX_PKT_REG, g_uEp1MaxPktSize);
						Outp32(DMA_FIFO_CNT_REG, g_uEp1MaxPktSize);
						Outp32(DMA_CNT_REG, g_uEp1MaxPktSize);
						Outp32(DMA_MEg_BASE_ADDR, uUploadAddr);
						Outp32(DMA_TOTAL_CNT1_REG, (U16)uUploadSize);
						Outp32(DMA_TOTAL_CNT2_REG, (U16)(uUploadSize>>16));
						Outp32(DMA_CON_REG, DMA_FLY_ENABLE|DMA_TX_START|USB_DMA_MODE);
					}
				}
				g_uDownloadFileSize=0;
				return;
			}
			else
			{
			    if(download_run==0)
   	    		{
					g_uDownloadAddress=tempDownloadAddress; 
	    		}
	    		else
	    		{
	    			RdPktEp3((U8 *)TempBuf, 8);
					if (ep3csr&(0x1<<4))
						fifoCntByte = fifoCnt * 2 -1;
					else
						fifoCntByte = fifoCnt * 2;
					DbgUsb(("downloadFileSize==0, 1'st BYTE_READ_CNT_REG : %x\n", fifoCntByte));
					g_uDownloadAddress=
						*((U8 *)(TempBuf+0))+
						(*((U8 *)(TempBuf+1))<<8)+
						(*((U8 *)(TempBuf+2))<<16)+
						(*((U8 *)(TempBuf+3))<<24);
	    		}
				if(download_run==0)
   	    		{
   	    			RdPktEp3((U8 *)TempBuf, 8);
					if (ep3csr&(0x1<<4))
						fifoCntByte = fifoCnt * 2 -1;
					else
						fifoCntByte = fifoCnt * 2;
   	    		}
					DbgUsb(("downloadFileSize==0, 1'st BYTE_READ_CNT_REG : %x\n", fifoCntByte));
					g_uDownloadFileSize=
						*((U8 *)(TempBuf+4))+
						(*((U8 *)(TempBuf+5))<<8)+
						(*((U8 *)(TempBuf+6))<<16)+
						(*((U8 *)(TempBuf+7))<<24);

				g_pDownPt=(U8 *)g_uDownloadAddress;
				DbgUsb(("downloadAddress : %x, downloadFileSize: %x\n", g_uDownloadAddress, g_uDownloadFileSize));
				
				RdPktEp3((U8 *)g_pDownPt, fifoCntByte-8); // The first 8-bytes are deleted.
			
				if (g_eOpMode == USB_CPU)
				{
					if (ep3csr & (0x2<<2))
					{
						Inp32(BYTE_READ_CNT_REG, fifoCnt);
						if (ep3csr&(0x1<<4))
							fifoCntByte = fifoCnt * 2 -1;
						else
							fifoCntByte = fifoCnt * 2;
						DbgUsb(("2'd BYTE_READ_CNT_REG : %x\n", fifoCntByte));
						RdPktEp3((U8 *)g_pDownPt, fifoCntByte);
					}
				}
			else
				{
						uDownloadFileSize = g_uDownloadFileSize-fifoCntByte;
					if (uDownloadFileSize > g_uEp3MaxPktSize)
					{
						Outp32(FCON, DMA_ENABLE);				// USB Dma Enable in Core Outside
						Outp32(INDEX_REG, EP3);					// OUT Direction  Host -> Device
						Outp32(DMA_IF_CON_REG, MAX_BURST_INCR16);
						Outp32(MAX_PKT_REG, g_uEp3MaxPktSize);
						Outp32(DMA_FIFO_CNT_REG, g_uEp3MaxPktSize);
						Outp32(DMA_CNT_REG, g_uEp3MaxPktSize);
						Outp32(DMA_MEg_BASE_ADDR, g_uDownloadAddress+fifoCntByte-8);
						uDownloadFileSize = (uDownloadFileSize/g_uEp3MaxPktSize)*g_uEp3MaxPktSize;
						
						Outp32(DMA_TOTAL_CNT1_REG, (U16)(uDownloadFileSize));
						Outp32(DMA_TOTAL_CNT2_REG, (U16)(uDownloadFileSize>>16));
						DbgUsb(("Out Direction DMA RX Start\n"));
						Delay(1);
						Outp32(DMA_CON_REG, DMA_FLY_ENABLE|DMA_RX_START|USB_DMA_MODE);
					}
					else
						g_eOpMode = USB_CPU;
				}
			}
		}

		else
		{	
			Inp32(EP_STATUS_REG, ep3csr);
			
			if (g_eOpMode == USB_CPU)
			{
				Inp32(BYTE_READ_CNT_REG, fifoCnt);
				if (ep3csr&(0x1<<4))
					fifoCntByte = fifoCnt * 2 -1;
				else
					fifoCntByte = fifoCnt * 2;
				DbgUsb(("downloadFileSize!=0, 1'st BYTE_READ_CNT_REG : %x\n", fifoCntByte));
				RdPktEp3((U8 *)g_pDownPt, fifoCntByte);
				if ((ep3csr & (0x2<<2)))
				{
					Inp32(BYTE_READ_CNT_REG, fifoCnt);
					if (ep3csr&(0x1<<4))
						fifoCntByte = fifoCnt * 2 -1;
					else
						fifoCntByte = fifoCnt * 2;
					DbgUsb(("2'd BYTE_READ_CNT_REG : %x\n", fifoCntByte));
					RdPktEp3((U8 *)g_pDownPt, fifoCntByte);
				
				}
			}
		}
		return;
	}
} 
#endif