📄 bsp.c
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/*
*********************************************************************************************************
*
* MICRIUM BOARD SUPPORT PACKAGE
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* BOARD SUPPORT PACKAGE (BSP) FUNCTIONS
*
* CSB ARM MAIN FILE
*
* Filename : bsp.c
* Version : V1.89
* Programmer(s) : Jean-Denis Hatier
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#include <includes.h>
#include <reg_AT91RM9200.h>
/*
*********************************************************************************************************
* DEFINES
*********************************************************************************************************
*/
/* C-Spy patch to unlock flash bus. */
#define BSP_FLASH_UNLOCK_ADDR (*(CPU_INT32U *)0x107FFFF0)
/* Micromonitor services entry point. */
#define BSP_uMON_ENTRY_POINT (*(CPU_INT32U *)0x10000020)
/* CSBx37 memory map. */
#define BSP_REMAP_ADDR 0x00000000
#define BSP_SRAM_ADDR 0x00200000
#define BSP_FLASH_ADDR 0x10000000
#define BSP_SDRAM_ADDR 0x20000000
/*
*********************************************************************************************************
TYPE DEFINITIONS
*********************************************************************************************************
*/
typedef void (*BSP_FNCT_PTR)(void);
/*
*********************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************
*/
static CPU_INT08U BSP_CSB_ARM_LED_RegImage;
/*
*********************************************************************************************************
* LOCAL FUNCTIONS PROTOTYPES
*********************************************************************************************************
*/
static void Tmr_TickHandler (void);
/*
*********************************************************************************************************
* GLOBAL FUNCTIONS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* BSP INITIALIZATION
*
* Description : BSP initialization. This function should be called by your application code before
* you make use of any of the functions found in this module.
*
* Arguments : None.
*
* Return(s) : None.
*
* Caller(s) : Application.
*********************************************************************************************************
*/
void BSP_Init (void)
{
CPU_DATA cpu_sr;
CPU_INT32U i;
BSP_CSB_ARM_LED_RegImage = 0;
OS_ENTER_CRITICAL(); /* Disable interrupts at processor level. */
*AT91C_AIC_IDCR = ~0; /* Disable interrupts at AIC level. */
BSP_FLASH_UNLOCK_ADDR = ~0; /* C-Spy patch to unlock flash bus. */
i = 0; /* Determine if remappable address range 0x00000000 */
while (*(CPU_INT32U*)(BSP_FLASH_ADDR + i) == /* to 0x0fffffff is mapped to FLASH or SRAM. */
*(CPU_INT32U*)(BSP_SRAM_ADDR + i)) {
i++;
}
if (*(CPU_INT32U*)(BSP_REMAP_ADDR + i) != /* If mapped to FLASH, remap it to SRAM. */
*(CPU_INT32U*)(BSP_SRAM_ADDR + i)) {
*AT91C_MC_RCR = AT91C_MC_RCB;
}
/* Activate i-cache. */
asm("MRC p15, 0, r0, c1, c0, 0");
asm("ORR r0, r0, #0x00001000");
asm("MCR p15, 0, r0, c1, c0, 0");
asm("nop");
asm("nop");
asm("nop");
/* Change BUS mode to synchronous. */
asm("MRC p15, 0, r0, c1, c0, 0");
asm("ORR r0, r0, #0x40000000");
asm("MCR p15, 0, r0, c1, c0, 0");
asm("nop");
asm("nop");
asm("nop");
/* Switch to the slow clock unless we already are. */
if (PMC_REG(PMC_MCKR)) {
PMC_REG(PMC_MCKR) = PMC_REG(PMC_MCKR) & ~PMC_MCKR_PRES_MASK;
PMC_REG(PMC_MCKR) = PMC_REG(PMC_MCKR) & ~PMC_MCKR_CSS_MASK;
}
/* Delay for slow clock synchronization. */
for (i = 0; i < 100; i++) {
;
}
/* Set new CPU clock speed (core clock). */
/* (3.6864 * 87 / 2 = 160.3584MHz). */
PMC_REG(PMC_PLLAR) = PMC_PLLAR_MUST_SET | /* This bit must be set according to the documentation. */
PMC_PLLAR_MUL(87-1) | /* Multiplier. */
PMC_PLLAR_OUT_150_240 | /* Select when PLL frequency is 150-240 MHz. */
PMC_PLLAR_DIV(2); /* Divider, */
/* Wait for PLLA lock bit. */
for (i = 0; i < 1000; i++) {
if (PMC_REG(PMC_SR) & PMC_INT_LCKA) {
break;
}
}
/* MCK = PLLA clock / 2 = 80.1792MHz. */
PMC_REG(PMC_MCKR) = PMC_MCKR_CSS_PLLA | /* Core Source = PLL A. */
PMC_MCKR_MDIV_2; /* MCK = Core / 2. */
/* Set Debug (serial) port to 38400bps. */
*AT91C_DBGU_BRGR = BSP_CLK_AT91RM9200_MASTER_HZ / (16 * BSP_DBGU_RATE);
/* Initialize monitor services. */
monConnect((int (*)())BSP_uMON_ENTRY_POINT, NULL, NULL);
LED_Init(); /* Initialize LEDs. */
OS_CPU_InitExceptVect(); /* Initialize exception vectors. */
OS_EXIT_CRITICAL(); /* Enable interrupts at processor level. */
}
/*
*********************************************************************************************************
* EXCEPTION HANDLER
*
* Arguments : None.
*********************************************************************************************************
*/
void OS_CPU_ExceptHndlr (CPU_DATA except_type)
{
BSP_FNCT_PTR pfnct;
CPU_INT32U *sp;
if (except_type == OS_CPU_ARM_EXCEPT_FIQ) {
pfnct = (BSP_FNCT_PTR)*AT91C_AIC_FVR; /* Read the FIQ handler from the AIC. */
while (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer. */
(*pfnct)(); /* Execute the handler. */
*AT91C_AIC_EOICR = ~0; /* End of handler. */
pfnct = (BSP_FNCT_PTR)*AT91C_AIC_FVR; /* Read the FIQ handler from the AIC. */
}
*AT91C_AIC_EOICR = ~0; /* End of handler. */
} else if (except_type == OS_CPU_ARM_EXCEPT_IRQ) {
pfnct = (BSP_FNCT_PTR)*AT91C_AIC_IVR; /* Read the IRQ handler from the AIC. */
while (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer. */
(*pfnct)(); /* Execute the handler. */
*AT91C_AIC_EOICR = ~0; /* End of handler. */
pfnct = (BSP_FNCT_PTR)*AT91C_AIC_IVR; /* Read the IRQ handler from the AIC. */
}
*AT91C_AIC_EOICR = ~0; /* End of handler. */
} else {
sp = (CPU_INT32U *)OSTCBCur->OSTCBStkPtr;
APP_TRACE_INFO(("\nCPU_ARM_EXCEPTION #%d trapped.\n", except_type));
APP_TRACE_INFO(("R0 : 0x%08x\n", *(sp + 0x01)));
APP_TRACE_INFO(("R1 : 0x%08x\n", *(sp + 0x02)));
APP_TRACE_INFO(("R2 : 0x%08x\n", *(sp + 0x03)));
APP_TRACE_INFO(("R3 : 0x%08x\n", *(sp + 0x04)));
APP_TRACE_INFO(("R4 : 0x%08x\n", *(sp + 0x05)));
APP_TRACE_INFO(("R5 : 0x%08x\n", *(sp + 0x06)));
APP_TRACE_INFO(("R6 : 0x%08x\n", *(sp + 0x07)));
APP_TRACE_INFO(("R7 : 0x%08x\n", *(sp + 0x08)));
APP_TRACE_INFO(("R8 : 0x%08x\n", *(sp + 0x09)));
APP_TRACE_INFO(("R9 : 0x%08x\n", *(sp + 0x0A)));
APP_TRACE_INFO(("R10 : 0x%08x\n", *(sp + 0x0B)));
APP_TRACE_INFO(("R11 : 0x%08x\n", *(sp + 0x0C)));
APP_TRACE_INFO(("R12 : 0x%08x\n", *(sp + 0x0D)));
APP_TRACE_INFO(("SP : 0x%08x\n", sp));
APP_TRACE_INFO(("LR : 0x%08x\n", *(sp + 0x0E)));
APP_TRACE_INFO(("PC : 0x%08x\n", *(sp + 0x0F)));
APP_TRACE_INFO(("CPSR: 0x%08x\n", *(sp + 0x00)));
/* Infinite loop on other exceptions. */
/* Should be replaced by other behavior (reboot, etc.) */
while (DEF_TRUE) {
;
}
}
}
/*
*********************************************************************************************************
* TICKER INITIALIZATION
*
* Description : This function is called to initialize uC/OS-II's tick source (typically a timer generating
* interrupts every 1 to 100 mS).
*
* We decided to use Timer #0 as the tick interrupt source.
*
* Arguments : None.
*********************************************************************************************************
*/
void Tmr_Init (void)
{
/* OS Timer is on interrupt #1. */
AIC_SVR_REG(1 * 4) = (CPU_INT32U)Tmr_TickHandler; /* Setup the interrupt vector for the tick ISR. */
AIC_SMR_REG(1 * 4) = AT91C_AIC_PRIOR_LOWEST | /* Level sensitive, low priority. */
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE;
*AT91C_AIC_IECR = DEF_BIT_01; /* Enable timer interrupt at AIC level. */
/* Initialize the timer to generate 100 Hz. */
*AT91C_ST_PIMR = BSP_CLK_AT91RM9200_SLOW_HZ / OS_TICKS_PER_SEC;
*AT91C_ST_IER = AT91C_ST_PITS; /* Enable timer interrupt at ST level. */
}
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