📄 csb_arm_ram_start.asm
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;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the start defined in the library, simply add your modified
; version to the workbench project.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment.
;
; $Revision: 1.56 $
;
;-----------------------------------------------------------------------------
;
; Naming covention of labels in this file:
;
; ?xxx - External labels only accessed from assembler.
; __xxx - External labels accessed from or defined in C.
; xxx - Labels local to one module (note: this file contains
; several modules).
; main - The starting point of the user program.
;
;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------
; Mode, correspords to bits 0-5 in CPSR
OS_CPU_ARM_MODE_MASK DEFINE 0x1F ; Bit mask for mode bits in CPSR
OS_CPU_ARM_MODE_USR DEFINE 0x10 ; User mode
OS_CPU_ARM_MODE_FIQ DEFINE 0x11 ; Fast Interrupt Request mode
OS_CPU_ARM_MODE_IRQ DEFINE 0x12 ; Interrupt Request mode
OS_CPU_ARM_MODE_SVC DEFINE 0x13 ; Supervisor mode
OS_CPU_ARM_MODE_ABT DEFINE 0x17 ; Abort mode
OS_CPU_ARM_MODE_UND DEFINE 0x1B ; Undefined Instruction mode
OS_CPU_ARM_MODE_SYS DEFINE 0x1F ; System mode
;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------
MODULE ?RESET
COMMON INTVEC:CODE:NOROOT(2)
PUBLIC __program_start
EXTERN ?start
EXTERN OS_CPU_ARM_ExceptResetHndlr
EXTERN OS_CPU_ARM_ExceptUndefInstrHndlr
EXTERN OS_CPU_ARM_ExceptSwiHndlr
EXTERN OS_CPU_ARM_ExceptPrefetchAbortHndlr
EXTERN OS_CPU_ARM_ExceptDataAbortHndlr
EXTERN OS_CPU_ARM_ExceptAddrAbortHndlr
EXTERN OS_CPU_ARM_ExceptIrqHndlr
EXTERN OS_CPU_ARM_ExceptFiqHndlr
CODE32
org 0x00
__program_start
b ?start
b ?OS_CPU_ARM_ExceptUndefInstrHndlr
b ?OS_CPU_ARM_ExceptSwiHndlr
b ?OS_CPU_ARM_ExceptPrefetchAbortHndlr
b ?OS_CPU_ARM_ExceptDataAbortHndlr
b ?OS_CPU_ARM_ExceptAddrAbortHndlr
b ?OS_CPU_ARM_ExceptIrqHndlr
b ?OS_CPU_ARM_ExceptFiqHndlr
?OS_CPU_ARM_ExceptResetHndlr
b OS_CPU_ARM_ExceptResetHndlr
?OS_CPU_ARM_ExceptUndefInstrHndlr
b OS_CPU_ARM_ExceptUndefInstrHndlr
?OS_CPU_ARM_ExceptSwiHndlr
b OS_CPU_ARM_ExceptSwiHndlr
?OS_CPU_ARM_ExceptPrefetchAbortHndlr
b OS_CPU_ARM_ExceptPrefetchAbortHndlr
?OS_CPU_ARM_ExceptDataAbortHndlr
b OS_CPU_ARM_ExceptDataAbortHndlr
?OS_CPU_ARM_ExceptAddrAbortHndlr
b OS_CPU_ARM_ExceptAddrAbortHndlr
?OS_CPU_ARM_ExceptIrqHndlr
b OS_CPU_ARM_ExceptIrqHndlr
?OS_CPU_ARM_ExceptFiqHndlr
b OS_CPU_ARM_ExceptFiqHndlr
LTORG
ENDMOD
;---------------------------------------------------------------
; ?START
;---------------------------------------------------------------
MODULE ?START
RSEG OS_CPU_ARM_MODE_FIQ_STK:DATA(2)
RSEG OS_CPU_ARM_MODE_IRQ_STK:DATA(2)
RSEG OS_CPU_ARM_MODE_ABT_STK:DATA(2)
RSEG OS_CPU_ARM_MODE_SVC_STK:DATA(2)
RSEG OS_CPU_ARM_MODE_UND_STK:DATA(2)
RSEG OS_CPU_ARM_MODE_SYS_STK:DATA(2)
RSEG ICODE:CODE:NOROOT(2)
PUBLIC ?start
EXTERN ?main
CODE32
?start
ldr r0, =0x00000000
mcr p15, 0, r0, c3, c0, 0 /* Grant manager access to all domains. */
nop
nop
nop
ldr r0, =0x00002001
mcr p15, 0, r0, c15, c1, 0 /* Allow access to all coprocessors. */
nop
nop
nop
ldr r0, =0x00000000
mcr p15, 0, r0, c8, c7, 0 /* Flush TLB's. */
mcr p15, 0, r0, c7, c7, 0 /* Flush Caches. */
mcr p15, 0, r0, c7, c10, 4 /* Flush Write Buffer. */
nop
nop
nop
/* Disable MMU. */
/* Disable all caches but i-cache. */
/* Disable write buffer. */
/* Change BUS mode to synchronous. */
ldr r0, =0x40001078
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
; SET-UP THE STACK-POINTERS FOR ALL OPERATING MODES.
; After a reset, the mode is ARM, System, interrupts
; disabled. The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker
; command file, and be declared above.
; FIQ mode.
mrs r0, cpsr ; Move CPSR to r0.
bic r0, r0, #OS_CPU_ARM_MODE_MASK ; Clear all mode bits.
orr r0, r0, #OS_CPU_ARM_MODE_FIQ ; Set FIQ mode bits.
msr CPSR_c, r0 ; Move back to CPSR.
; Initialize the stack ptr.
ldr sp, =SFE(OS_CPU_ARM_MODE_FIQ_STK) & 0xFFFFFFF8
; IRQ mode.
mrs r0, cpsr ; Move CPSR to r0.
bic r0, r0, #OS_CPU_ARM_MODE_MASK ; Clear all mode bits.
orr r0, r0, #OS_CPU_ARM_MODE_IRQ ; Set IRQ mode bits.
msr CPSR_c, r0 ; Move back to CPSR.
; Initialize the stack ptr.
ldr sp, =SFE(OS_CPU_ARM_MODE_IRQ_STK) & 0xFFFFFFF8
; Abort mode.
mrs r0, cpsr ; Move CPSR to r0.
bic r0, r0, #OS_CPU_ARM_MODE_MASK ; Clear all mode bits.
orr r0, r0, #OS_CPU_ARM_MODE_ABT ; Set Abort mode bits.
msr CPSR_c, r0 ; Move back to CPSR.
; Initialize the stack ptr.
ldr sp, =SFE(OS_CPU_ARM_MODE_ABT_STK) & 0xFFFFFFF8
; Undef mode.
mrs r0, cpsr ; Move CPSR to r0.
bic r0, r0, #OS_CPU_ARM_MODE_MASK ; Clear all mode bits.
orr r0, r0, #OS_CPU_ARM_MODE_UND ; Set Undef mode bits.
msr CPSR_c, r0 ; Move back to CPSR.
; Initialize the stack ptr.
ldr sp, =SFE(OS_CPU_ARM_MODE_UND_STK) & 0xFFFFFFF8
; System mode.
mrs r0, cpsr ; Move CPSR to r0.
bic r0, r0, #OS_CPU_ARM_MODE_MASK ; Clear all mode bits.
orr r0, r0, #OS_CPU_ARM_MODE_SYS ; Set System mode bits.
msr CPSR_c, r0 ; Move back to CPSR.
; Initialize the stack ptr.
ldr sp, =SFE(OS_CPU_ARM_MODE_SYS_STK) & 0xFFFFFFF8
; Supervisor mode.
mrs r0, cpsr ; Move CPSR to r0.
bic r0, r0, #OS_CPU_ARM_MODE_MASK ; Clear all mode bits.
orr r0, r0, #OS_CPU_ARM_MODE_SVC ; Set Supervisor mode bits.
msr CPSR_c, r0 ; Move back to CPSR.
; Initialize the stack ptr.
ldr sp, =SFE(OS_CPU_ARM_MODE_SVC_STK) & 0xFFFFFFF8
; Jump to main().
bl ?main
; The C code should never return.
b ?start
LTORG
ENDMOD
END
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