📄 os_cpu_a.s
字号:
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptResetHndlr:
@ LR offset to return from this exception: 0.
@ (there is no way to return from a RESET exception).
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_RESET @ Set exception ID to OS_CPU_ARM_EXCEPT_RESET.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ UNDEFINED INSTRUCTION EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptUndefInstrHndlr:
@ LR offset to return from this exception: 0.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_UNDEF_INSTR @ Set exception ID to OS_CPU_ARM_EXCEPT_UNDEF_INSTR.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ SOFTWARE INTERRUPT EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptSwiHndlr:
@ LR offset to return from this exception: 0.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_SWI @ Set exception ID to OS_CPU_ARM_EXCEPT_SWI.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ PREFETCH ABORT EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptPrefetchAbortHndlr:
SUB LR, LR, #4 @ LR offset to return from this exception: -4.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_PREFETCH_ABORT @ Set exception ID to OS_CPU_ARM_EXCEPT_PREFETCH_ABORT.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ DATA ABORT EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptDataAbortHndlr:
SUB LR, LR, #8 @ LR offset to return from this exception: -8.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_DATA_ABORT @ Set exception ID to OS_CPU_ARM_EXCEPT_DATA_ABORT.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ ADDRESS ABORT EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptAddrAbortHndlr:
SUB LR, LR, #8 @ LR offset to return from this exception: -8.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_ADDR_ABORT @ Set exception ID to OS_CPU_ARM_EXCEPT_ADDR_ABORT.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ INTERRUPT REQUEST EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptIrqHndlr:
SUB LR, LR, #4 @ LR offset to return from this exception: -4.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_IRQ @ Set exception ID to OS_CPU_ARM_EXCEPT_IRQ.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ FAST INTERRUPT REQUEST EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptFiqHndlr:
SUB LR, LR, #4 @ LR offset to return from this exception: -4.
STMFD SP!, {R0-R12, LR} @ Push working registers.
MOV R3, LR @ Save link register.
MOV R0, #OS_CPU_ARM_EXCEPT_FIQ @ Set exception ID to OS_CPU_ARM_EXCEPT_FIQ.
B OS_CPU_ARM_ExceptHndlr @ Branch to global exception handler.
@********************************************************************************************************
@ GLOBAL EXCEPTION HANDLER
@
@ Register Usage: R0 Exception Type
@ R1 Exception's SPSR
@ R2 Old CPU mode
@ R3 Return PC
@********************************************************************************************************
OS_CPU_ARM_ExceptHndlr:
MRS R1, SPSR @ Save CPSR (i.e. exception's SPSR).
@ DETERMINE IF WE INTERRUPTED A TASK OR ANOTHER LOWER PRIORITY EXCEPTION:
@ SPSR.Mode = SVC : task,
@ SPSR.Mode = FIQ, IRQ, ABT, UND : other exceptions,
@ SPSR.Mode = USR : *unsupported state*.
AND R2, R1, #OS_CPU_ARM_MODE_MASK
CMP R2, #OS_CPU_ARM_MODE_SVC
BNE OS_CPU_ARM_ExceptHndlr_BreakExcept
@********************************************************************************************************
@ EXCEPTION HANDLER: TASK INTERRUPTED
@
@ Register Usage: R0 Exception Type
@ R1 Exception's SPSR
@ R2 Exception's CPSR
@ R3 Return PC
@ R4 Exception's SP
@********************************************************************************************************
OS_CPU_ARM_ExceptHndlr_BreakTask:
MRS R2, CPSR @ Save exception's CPSR.
MOV R4, SP @ Save exception's stack pointer.
@ Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
@ SAVE TASK'S CONTEXT ONTO TASK'S STACK:
STMFD SP!, {R3} @ Push task's PC,
STMFD SP!, {LR} @ Push task's LR,
STMFD SP!, {R5-R12} @ Push task's R12-R5,
LDMFD R4!, {R5-R9} @ Move task's R4-R0 from exception stack to task's stack.
STMFD SP!, {R5-R9}
STMFD SP!, {R1} @ Push task's CPSR (i.e. exception SPSR).
@ if (OSRunning == 1)
LDR R1, =OSRunning
LDRB R1, [R1]
CMP R1, #1
BNE OS_CPU_ARM_ExceptHndlr_BreakTask_1
@ HANDLE NESTING COUNTER:
LDR R3, =OSIntNesting @ OSIntNesting++;
LDRB R4, [R3]
ADD R4, R4, #1
STRB R4, [R3]
LDR R3, =OSTCBCur @ OSTCBCur->OSTCBStkPtr = SP;
LDR R4, [R3]
STR SP, [R4]
OS_CPU_ARM_ExceptHndlr_BreakTask_1:
MSR CPSR_cxsf, R2 @ RESTORE INTERRUPTED MODE.
@ EXECUTE EXCEPTION HANDLER:
LDR R1, =OS_CPU_ExceptHndlr @ OS_CPU_ExceptHndlr(except_type = R0);
MOV LR, PC
BX R1
@ Adjust exception stack pointer. This is needed because
@ exception stack is not used when restoring task context.
ADD SP, SP, #(14 * 4)
@ Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
@ Call OSIntExit(). This call MAY never return if a ready
@ task with higher priority than the interrupted one is
@ found.
LDR R0, =OSIntExit
MOV LR, PC
BX R0
@ RESTORE NEW TASK'S CONTEXT:
LDMFD SP!, {R0} @ Pop new task's CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ @ Pop new task's context.
@********************************************************************************************************
@ EXCEPTION HANDLER: EXCEPTION INTERRUPTED
@
@ Register Usage: R0 Exception Type
@ R1
@ R2
@ R3
@********************************************************************************************************
OS_CPU_ARM_ExceptHndlr_BreakExcept:
MRS R2, CPSR @ Save exception's CPSR.
@ Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
@ HANDLE NESTING COUNTER:
LDR R3, =OSIntNesting @ OSIntNesting++;
LDRB R4, [R3]
ADD R4, R4, #1
STRB R4, [R3]
MSR CPSR_cxsf, R2 @ RESTORE INTERRUPTED MODE.
@ EXECUTE EXCEPTION HANDLER:
LDR R3, =OS_CPU_ExceptHndlr @ OS_CPU_ExceptHndlr(except_type = R0);
MOV LR, PC
BX R3
@ Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
@ HANDLE NESTING COUNTER:
LDR R3, =OSIntNesting @ OSIntNesting--;
LDRB R4, [R3]
SUB R4, R4, #1
STRB R4, [R3]
MSR CPSR_cxsf, R2 @ RESTORE INTERRUPTED MODE.
@ RESTORE OLD CONTEXT:
LDMFD SP!, {R0-R12, PC}^ @ Pull working registers and return from exception.
.ltorg
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -