1001.pci.patch

sm86xx内核源包括补丁（ GPL ）的

+/* Status of PCI host */
+static int pci_active = 0;
+
+static int __init tangox_pci_init(void)
+{
+	void __iomem *pci_io_base;
+	unsigned long memsize, regsize, membase, max_dma_size;
+	u32 data;
+	int i;
+
+	/* don't do anything if pci support is not enabled in xenv nor is it by cmd line */
+	if (!pci_enabled) {
+		return 0;
+	} else if (!tangox_pci_host_enabled()) {
+		printk(KERN_NOTICE "PCI: pci host support disabled\n");
+		return 0;
+	} 
+
+	printk("PCI: Initializing SMP863x/SMP865x PCI host controller\n");
+
+	/*
+	 * Enable pci host support
+	 */
+	WR_HOST_REG32(PCI_chip_is_host, 0); /* Reset PCI host */
+	udelay(1000);
+	WR_HOST_REG32(PCI_chip_is_host, 1);
+
+	/*
+	 * HOST_REG1 :
+	 * [31:16] : # of PCI retry cycle = 0xffff (default = 0xff)
+	 * [8] : host Super Request = 0
+	 * [3:0] arbitration level = 0x00 (Level 1)
+	 */
+	WR_HOST_REG32(PCI_host_reg1, 0xffff0000 | PCIEM86XX_ARBITER_LEVEL);
+
+	/*
+	 * PCI_CTRL1 :
+	 * [17] : enable "Memory Read Multiple" and "Memory Read Line"
+	 * [16] [7:0] : enable "prefetch" for PCI slave regions 2..7
+	 * [17] : Always enabled
+	 * [18] : additional bit for Tango. Long PCI memory read burst
+	 */
+	WR_HOST_REG32(PCI_pcictrl_reg1, 0x00030000);
+
+	/*
+	 * PCI_CTRL2 :
+	 * [18] : fast back-to-back capable = 0 (default)
+	 * [17] : read FIFO level = 1 (8 level deep, default)
+	 * [16] : discard timer enable = 1 (default)
+	 * [15:8] : subs latency = 0x06 (default = 0x08)
+	 * [7:0] : initial latency = 0x0d (default = 0x0b)
+	 */
+	WR_HOST_REG32(PCI_pcictrl_reg2, 0x0003060d);
+
+	/*
+	 * PCI_CTRL3 :
+	 * [16] : slave abort clear = 0
+	 * [10:8] : abort interrupt enable = 0 (default)
+	 * [2:0] : abort status = 0
+	 */
+	WR_HOST_REG32(PCI_pcictrl_reg3, 0);
+
+	/* clear any pending PCI bus fault */
+	if ((RD_HOST_REG8(PCI_host_reg2 + 3) >> 1) & 0x3) {
+		WR_HOST_REG8(PCI_host_reg2 + 3, 1);
+		WR_HOST_REG8(PCI_host_reg2 + 3, 0);
+	}
+
+	/* Setting pci_configuration_vld */
+	WR_HOST_REG8(PCI_host_reg2 + 2, 1);
+
+	/* grant timeout */
+	WR_HOST_REG32(PCI_host_reg3, PCIEM86XX_ARBITER_GRANTTIMEOUT);
+	WR_HOST_REG32(PCI_host_reg5,
+		      PCIEM86XX_ARBITER_GRANTTIMEOUT & 0x000000ff);
+
+	/* initialize arbiter */
+	WR_HOST_REG32(PCI_host_reg4, 0);
+
+
+	/*
+	 * remap iorange and give port base to linux.
+	 */
+	pci_io_base = ioremap(MEMORY_BASE_PCI_IO, MEMORY_SIZE_PCI_IO);
+	set_io_port_base((unsigned long)pci_io_base - MEMORY_BASE_PCI_IO);
+
+	printk("PCI: Remapped PCI I/O space 0x%08lx to 0x%p, size %u kB\n",
+	       MEMORY_BASE_PCI_IO, pci_io_base, MEMORY_SIZE_PCI_IO / 1024);
+
+	/*
+	 * remap configuration space also
+	 */
+	tangox_pci_config_base = ioremap(MEMORY_BASE_PCI_CONFIG,
+					 MEMORY_SIZE_PCI_CONFIG);
+
+	printk("PCI: Remapped PCI config space 0x%08lx to 0x%p, size %u kB\n",
+	       MEMORY_BASE_PCI_CONFIG, tangox_pci_config_base,
+	       MEMORY_SIZE_PCI_CONFIG / 1024);
+
+	memset(&enabled_devices, 0, sizeof (enabled_devices));
+	for (i = 1; i < PCIEM86XX_IDSEL_MAX; i++) {
+		if (tangox_pcidev_enabled(i)) {
+			enabled_devices[i] = 1;
+		} else {
+			printk("PCI: device %d disabled\n", i);
+		}
+	}
+
+	/*
+	 * check that we can probe the EM8XXX at id 0
+	 */
+	if (tangox_cfg_read32(tangox_pci_config_base, &data)) {
+		printk("PCI: Can't initialize EM86XX as a PCI slave\n");
+		memset(&enabled_devices, 0, sizeof (enabled_devices));
+		return 1;
+	}
+
+	/*
+	 * configure it as a PCI slave
+	 *
+	 * set PCI memory size to maximum, so the PCI memory will cover the
+	 * whole memory if the total DRAM size is smaller than 112MB/896MB (Tango2/Tango3).
+	 * For Tango2, maximum = 128MB => 16MB per region => DMA memory = 16 * 7 = 112MB
+	 * For Tango3, maximum = 1024MB => 128MB per region => DMA memory = 128 * 7 = 896MB
+	 * But the current code doesn't care 2nd DRAM controller.
+	 */
+	WR_HOST_REG8(PCI_REG3, MAX_LOG2_PCIMEM_MAP);
+
+	memsize = RD_HOST_REG32(PCI_REG3) & 0x07;
+
+#ifdef CONFIG_TANGO2
+	memsize = 1 << memsize;  /* from 1MB to 128MB */
+#elif defined(CONFIG_TANGO3)
+	memsize = 1 << (memsize + 3); /* from 8MB to 1024MB */
+#else
+#error Unsupported chip!
+#endif
+
+	/* get memory size in bytes / 8 */
+	regsize = (memsize << 20) >> 3; /* regsize in MB */
+
+	/* pci command */
+	__raw_writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
+		     (void *)(tangox_pci_config_base + PCI_COMMAND));
+
+	/* base address 0 */
+	g_pcimem_busaddr = PCIBIOS_MIN_MEM_EM86XX - MEMORY_BASE_PCI_MEMORY;
+	__raw_writel(g_pcimem_busaddr,
+		     (void *)(tangox_pci_config_base + PCI_BASE_ADDRESS_0));
+
+	/*
+	 * PCI slave access
+	 * region 0 (R) : Configuration area
+	 * region 1 - 7: mapped to DRAM starting from DRAM_BASE */
+	g_pcimem_busaddr += (regsize * 1);
+	printk("PCI: Configured SMP863x/SMP865x as PCI slave with %ldMB "
+	       "PCI memory\n", memsize);
+	membase = CPHYSADDR(em8xxx_kmem_start);
+	max_dma_size = (unsigned long)MAX_DMA_ADDRESS - em8xxx_kmem_start;
+	g_pcimem_physaddr = membase;
+	g_pcimem_physaddr_end = g_pcimem_physaddr + em8xxx_kmem_size;
+
+        for (i = 1; (i < 8) && (max_dma_size > 0); ++i) {
+		/* PCI region base registers should contain low address */
+		WR_HOST_REG32(PCI_REGION_0_BASE + (i * 4), tangox_dma_address(CPHYSADDR(membase)));
+		membase += regsize; 
+		max_dma_size -= regsize;
+	}
+
+	if (g_pcimem_physaddr_end > membase)
+		g_pcimem_physaddr_end = membase;
+        printk("PCI: Region size is %ldKB\n", regsize >> 10);
+        printk("PCI: Map DMA memory 0x%08lx-0x%08lx for PCI at 0x%08lx\n",
+	       g_pcimem_physaddr, g_pcimem_physaddr_end, g_pcimem_busaddr);
+
+	/*
+	 * register the PCI bus fault interrupt
+	 */
+	request_irq(PCIEM86XX_PCIFAULT_INTR, pci_busfault_intr,
+		    SA_SHIRQ, "tangox_pci_fault", NULL);
+
+	/* finally register pci controller */
+	register_pci_controller(&tangox_controller);
+
+	pci_active = 1;
+
+	return 0;
+}
+
+arch_initcall(tangox_pci_init);
+
+/* For shutting down all PCI devices on this bus */
+void tangox_pci_shutdown(void)
+{
+	struct pci_bus *bus = tangox_controller.bus;
+        struct list_head *list;
+
+	if (pci_active) {
+		list_for_each(list, &bus->devices) {
+			pci_disable_device(pci_dev_b(list));
+		}
+	}
+}
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/arch/mips/tangox/setup.c linux-2.6.15/arch/mips/tangox/setup.c
--- linux-2.6.15.ref/arch/mips/tangox/setup.c	2007-06-20 12:06:10.000000000 -0700
+++ linux-2.6.15/arch/mips/tangox/setup.c	2007-06-20 12:07:42.000000000 -0700
@@ -40,6 +40,9 @@
 #define WR_CPU_REG32(r, v)	\
 		gbus_writel(REG_BASE_cpu_block + (r), (v))
 
+#ifdef CONFIG_PCI
+extern void tangox_pci_shutdown(void);
+#endif
 
 /*
  * we use xrpc to reboot
@@ -76,6 +79,9 @@
         /* Disable timer */
 	WR_CPU_REG32(CPU_time0_clr, 1);
 #endif
+#ifdef CONFIG_PCI
+	tangox_pci_shutdown();
+#endif
 
 #if (defined(CONFIG_TANGO2) && (EM86XX_REVISION > 3)) || defined(CONFIG_TANGO3)
 	/* Resetting TangoX EHCI */
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/drivers/pci/quirks.c linux-2.6.15/drivers/pci/quirks.c
--- linux-2.6.15.ref/drivers/pci/quirks.c	2006-01-25 20:51:36.000000000 -0800
+++ linux-2.6.15/drivers/pci/quirks.c	2007-06-20 12:07:42.000000000 -0700
@@ -24,6 +24,13 @@
 #include <linux/acpi.h>
 #include "pci.h"
 
+int pci_pci_problems = 0;
+int isa_dma_bridge_buggy = 0;		/* Exported */
+int pcie_mch_quirk = 0;
+
+/* For Sigma Designs' TangoX, no quirks should be needed, at least for now */
+#ifndef CONFIG_TANGOX
+
 /* Deal with broken BIOS'es that neglect to enable passive release,
    which can cause problems in combination with the 82441FX/PPro MTRRs */
 static void __devinit quirk_passive_release(struct pci_dev *dev)
@@ -50,7 +57,6 @@
     
     This appears to be BIOS not version dependent. So presumably there is a 
     chipset level fix */
-int isa_dma_bridge_buggy;		/* Exported */
     
 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
 {
@@ -71,8 +77,6 @@
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs );
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs );
 
-int pci_pci_problems;
-
 /*
  *	Chipsets where PCI->PCI transfers vanish or hang
  */
@@ -1178,8 +1182,6 @@
 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
 
 
-int pcie_mch_quirk;
-
 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
 {
 	pcie_mch_quirk = 1;
@@ -1257,6 +1259,7 @@
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
 
+#endif /* !CONFIG_TANGOX */
 
 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
 {
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/include/asm-mips/tango2/tango2_pci.h linux-2.6.15/include/asm-mips/tango2/tango2_pci.h
--- linux-2.6.15.ref/include/asm-mips/tango2/tango2_pci.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.15/include/asm-mips/tango2/tango2_pci.h	2007-06-20 12:07:42.000000000 -0700
@@ -0,0 +1,66 @@
+
+#ifndef __TANGO2_PCI_H
+#define __TANGO2_PCI_H
+
+#include <asm/tango2/hardware.h>
+#include <asm/tango2/tango2_gbus.h>
+
+#define PCIEM86XX_PCIFAULT_INTR		((IRQ_CONTROLLER_IRQ_BASE) + \
+						(LOG2_CPU_PCI_FAULT_INT))
+
+#define PCIEM86XX_ARBITER_LEVEL		0x00
+#define PCIEM86XX_ARBITER_GRANTTIMEOUT	0x10101010
+
+#define PCIEM86XX_IDSEL_MAX		0x05
+#define PCIEM86XX_IDSEL_BITS		0x03
+
+/*
+ * helpers to access host interface registers
+ */
+#define RD_HOST_REG32(r)	\
+		gbus_readl(REG_BASE_host_interface + (r))
+
+#define WR_HOST_REG32(r, v)	\
+		gbus_writel(REG_BASE_host_interface + (r), (v))
+
+#define RD_HOST_REG8(r)	\
+		gbus_readb(REG_BASE_host_interface + (r))
+
+#define WR_HOST_REG8(r, v)	\
+		gbus_writeb(REG_BASE_host_interface + (r), (v))
+
+
+/*
+ * read/write data  from/to the configuration space.  The  only way to
+ * know if there is a device is by checking that we did not generate a
+ * bus fault interrupt, so we need to mask them during the access.
+ */
+#define BUILD_TANGOX_CFG_ACCESS(pfx, __x)				\
+static inline int tangox_cfg_##pfx(void __iomem *addr, u32 *data)	\
+{									\
+	unsigned long flags, status;					\
+									\
+	local_irq_save(flags);						\
+									\
+	__x;								\
+	status = (RD_HOST_REG8(PCI_host_reg2 + 3) >> 1) & 0x3;		\
+	if (status) {							\
+		WR_HOST_REG8(PCI_host_reg2 + 3, 1);			\
+		WR_HOST_REG8(PCI_host_reg2 + 3, 0);			\
+		local_irq_restore(flags);				\
+		return 1;						\
+	}								\
+									\
+	local_irq_restore(flags);					\
+	return 0;							\
+}
+
+BUILD_TANGOX_CFG_ACCESS(read8, *data = readb(addr) & 0xff)
+BUILD_TANGOX_CFG_ACCESS(read16, *data = readw(addr) & 0xffff)
+BUILD_TANGOX_CFG_ACCESS(read32, *data = readl(addr))
+BUILD_TANGOX_CFG_ACCESS(write8, writeb(*data & 0xff, addr))
+BUILD_TANGOX_CFG_ACCESS(write16, writew(*data & 0xffff, addr))
+BUILD_TANGOX_CFG_ACCESS(write32, writel(*data, addr))
+
+#endif
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/include/asm-mips/tango3/tango3_pci.h linux-2.6.15/include/asm-mips/tango3/tango3_pci.h
--- linux-2.6.15.ref/include/asm-mips/tango3/tango3_pci.h	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.15/include/asm-mips/tango3/tango3_pci.h	2007-06-20 12:07:42.000000000 -0700
@@ -0,0 +1,66 @@
+
+#ifndef __TANGO3_PCI_H
+#define __TANGO3_PCI_H
+
+#include <asm/tango3/hardware.h>
+#include <asm/tango3/tango3_gbus.h>
+
+#define PCIEM86XX_PCIFAULT_INTR		((IRQ_CONTROLLER_IRQ_BASE) + \
+						(LOG2_CPU_PCI_FAULT_INT))
+
+#define PCIEM86XX_ARBITER_LEVEL		0x00
+#define PCIEM86XX_ARBITER_GRANTTIMEOUT	0x10101010
+
+#define PCIEM86XX_IDSEL_MAX		0x05
+#define PCIEM86XX_IDSEL_BITS		0x03
+
+/*
+ * helpers to access host interface registers
+ */
+#define RD_HOST_REG32(r)	\
+		gbus_readl(REG_BASE_host_interface + (r))
+
+#define WR_HOST_REG32(r, v)	\
+		gbus_writel(REG_BASE_host_interface + (r), (v))
+
+#define RD_HOST_REG8(r)	\
+		gbus_readb(REG_BASE_host_interface + (r))
+
+#define WR_HOST_REG8(r, v)	\
+		gbus_writeb(REG_BASE_host_interface + (r), (v))
+
+
+/*
+ * read/write data  from/to the configuration space.  The  only way to
+ * know if there is a device is by checking that we did not generate a
+ * bus fault interrupt, so we need to mask them during the access.
+ */
+#define BUILD_TANGOX_CFG_ACCESS(pfx, __x)				\
+static inline int tangox_cfg_##pfx(void __iomem *addr, u32 *data)	\
+{									\
+	unsigned long flags, status;					\
+									\
+	local_irq_save(flags);						\
+									\
+	__x;								\
+	status = (RD_HOST_REG8(PCI_host_reg2 + 3) >> 1) & 0x3;		\
+	if (status) {							\
+		WR_HOST_REG8(PCI_host_reg2 + 3, 1);			\
+		WR_HOST_REG8(PCI_host_reg2 + 3, 0);			\
+		local_irq_restore(flags);				\
+		return 1;						\
+	}								\
+									\
+	local_irq_restore(flags);					\
+	return 0;							\
+}
+
+BUILD_TANGOX_CFG_ACCESS(read8, *data = readb(addr) & 0xff)
+BUILD_TANGOX_CFG_ACCESS(read16, *data = readw(addr) & 0xffff)
+BUILD_TANGOX_CFG_ACCESS(read32, *data = readl(addr))
+BUILD_TANGOX_CFG_ACCESS(write8, writeb(*data & 0xff, addr))
+BUILD_TANGOX_CFG_ACCESS(write16, writew(*data & 0xffff, addr))
+BUILD_TANGOX_CFG_ACCESS(write32, writel(*data, addr))
+
+#endif
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/README.1001.pci.patch linux-2.6.15/README.1001.pci.patch
--- linux-2.6.15.ref/README.1001.pci.patch	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.15/README.1001.pci.patch	2007-06-20 12:08:29.000000000 -0700
@@ -0,0 +1,19 @@
+Feature:
+--------
+PCI host support for SMP863x and SMP865x
+
+Prerequisite patch numbers:
+---------------------------
+0000
+1000
+
+Primary author:
+---------------
+External (YH Lin)
+
+Related to which chip version SMP86xx xx=?
+-----------------------------------------
+Tango2 ES6/RevA or above, or Tango3 ES1 or above
+
+(linux patches) which CONFIG_... are provided:
+----------------------------------------------