1013.frequency.patch

sm86xx内核源包括补丁（ GPL ）的

+	fast_iob();
+#ifdef FC_DEBUG
+	uart_puts("Stop listening to WOL packet.\n");
+#endif
+	udelay(1000);
+
+	return(0);
+}
+
+unsigned long eth_poll_key(void)
+{
+	unsigned long wol_stat = *((volatile unsigned long *)KSEG1ADDR(REG_BASE_host_interface + WOL_CTRL));
+	if ((wol_stat & 0x60) != 0) {
+		/* clear the status */
+		*((volatile unsigned long *)KSEG1ADDR(REG_BASE_host_interface + WOL_CTRL)) = 0x60;
+		fast_iob();
+#ifdef FC_DEBUG
+		uart_puts("Got WOL packet\n");
+#endif
+		return(1);
+	} else
+		return(0);
+}
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/arch/mips/tangox/fctrl/lib/fc/fc.ld.script linux-2.6.15/arch/mips/tangox/fctrl/lib/fc/fc.ld.script
--- linux-2.6.15.ref/arch/mips/tangox/fctrl/lib/fc/fc.ld.script	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.15/arch/mips/tangox/fctrl/lib/fc/fc.ld.script	2007-07-06 10:25:03.000000000 -0700
@@ -0,0 +1,59 @@
+OUTPUT_ARCH(mips)
+ENTRY(__frequency_set)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    _ftext = . ;
+    fc.o (.text)		/* entry point		    */
+    *(.text)
+    _ecode = ABSOLUTE(.) ;	/* End of code 			    */
+    *(.rodata)
+    *(.rodata.*)
+    *(.rodata1)
+  } =0
+  _etext = .;
+
+  . = ALIGN(8);
+  _sdata = .;
+
+  .data :
+  AT( _sdata )
+  {
+    _fdata = .;	/* Start of initialised data	    */
+    *(.data)
+   
+    . = ALIGN(8);
+
+    _gp = . + 0x7ff0; /* Base of small data		    */
+
+    *(.lit8) 
+    *(.lit4) 
+    *(.sdata) 
+
+    . = ALIGN(8);
+
+    _edata  = .;	/* End of initialised data	    */
+  }
+
+  _fbss = .;
+  .sbss : 
+  { 
+    *(.sbss) 
+    *(.scommon)
+  }
+  .bss :
+  {
+    *(.bss)
+    *(COMMON)
+  }
+  . = ALIGN(256);
+  _end = . ;
+
+  /* Sections to be discarded */
+  /DISCARD/ :
+  {
+    	*(.reginfo)
+  }
+}
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/arch/mips/tangox/fctrl/lib/fc/fc.S linux-2.6.15/arch/mips/tangox/fctrl/lib/fc/fc.S
--- linux-2.6.15.ref/arch/mips/tangox/fctrl/lib/fc/fc.S	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.15/arch/mips/tangox/fctrl/lib/fc/fc.S	2007-07-06 10:25:03.000000000 -0700
@@ -0,0 +1,321 @@
+
+/* 
+ * Assembly routine to implement the change of frequency
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifdef CONFIG_TANGO2
+#include <asm/tango2/emhwlib_registers_tango2.h>
+#include <asm/tango2/emhwlib_dram_tango2.h>
+#include <asm/tango2/emhwlib_lram.h>
+#elif defined(CONFIG_TANGO3)
+#include <asm/tango3/emhwlib_registers_tango3.h>
+#include <asm/tango3/emhwlib_dram_tango3.h>
+#include <asm/tango2/emhwlib_lram.h>
+#endif
+
+#ifndef INPUT_TABLE_SIZE
+#define INPUT_TABLE_SIZE    32
+#endif
+
+#ifdef WITH_IR
+#define IR_FLAG  1
+#else
+#define IR_FLAG  0
+#endif
+
+#ifdef WITH_FIP
+#define FIP_FLAG  2
+#else
+#define FIP_FLAG  0
+#endif
+
+#ifdef WITH_ETH
+#define ETH_FLAG  4
+#else
+#define ETH_FLAG  0
+#endif
+
+#define KSEG1_ADDR 0xa0000000
+#define DELAY(reg1,reg2,value) \
+		li reg1,value;	\
+		move reg2,zero;	\
+	1: 	bne reg1,reg2,1b;	\
+		addiu reg2,reg2,1;
+
+LEAF(__frequency_set)
+
+	.align	4
+entry_point:
+	.word	_start
+params_start:
+	.word	param_area
+ir_table:
+	.word	ir_keys
+fip_table:
+	.word	fip_keys
+return_key:
+	.word	0
+time_elapse:
+	.word	0
+input_ctrl:
+	.word	(IR_FLAG | FIP_FLAG | ETH_FLAG)
+
+	.align	4
+param_area:
+setting_pll3:
+	.word   0	/* pll3 */
+setting_pll2:
+	.word   0	/* pll2 */
+setting_pll1:
+	.word   0	/* pll1 */
+setting_pll0:
+	.word   0	/* pll0 */
+setting_mux:
+	.word   0	/* mux */
+setting_d0cfg:
+	.word   0	/* d0cfg */
+setting_d0delay:
+	.word   0	/* d0delay */
+setting_d1cfg:
+	.word   0	/* d1cfg */
+setting_d1delay:
+	.word   0	/* d1delay */
+setting_standby:
+	.word	0	/* standby mode */
+setting_desc:
+	.word	0	/* desc */
+
+	.align	4
+ir_keys:
+	.fill	INPUT_TABLE_SIZE
+
+fip_keys:
+	.fill	INPUT_TABLE_SIZE
+
+	/* all cache should be flushed (i.e. written back), interrupt should be disabled at this point */
+	/* a0 = standby mode (or not) */
+
+	.align	5
+	.set noreorder
+	.set mips32r2
+
+old_pll3:
+	.word	0
+old_pll1:
+	.word	0
+old_mux:
+	.word	0
+
+	.align	4
+_start:
+set_dram_auto_refesh:
+	/* set DRAM0/1 to auto-refresh mode */
+	li	t6,KSEG1_ADDR+REG_BASE_dram_controller_0+G2L_RESET_CONTROL
+	li	t4,KSEG1_ADDR+REG_BASE_dram_controller_0+DRAM_dunit_delay0_ctrl
+	li	t7,KSEG1_ADDR+REG_BASE_dram_controller_1+G2L_RESET_CONTROL
+	li	t5,KSEG1_ADDR+REG_BASE_dram_controller_1+DRAM_dunit_delay0_ctrl
+	addiu	t3,zero,1
+	sw	t3,0(t6)
+	sw	t3,0(t7)
+	sync
+
+	move	t3,zero
+	lui	t3,0x8000
+1:
+	lw	t0,0(t4)  /* need the MSB of delay0_ctrl to be set */
+	lw	t1,0(t5)
+	and	t0,t0,t3
+	and	t0,t0,t1
+	beq	t0,zero,1b
+	nop
+
+set_new_freq:
+	/* set CPU/SYS/DSP to new divider value */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_sysclk_mux
+	la	t1,setting_mux
+	la	t3,old_mux
+	lw	t2,0(t0)
+	sw	t2,0(t3)
+	lw	t2,0(t1)
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,255)
+
+	/* Detach PLL from MUX, assumed it's been attached before */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_sysclk_mux
+	la	t1,setting_mux
+	lw	t2,0(t1)
+	addiu	t2,t2,-1
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,255)
+	
+	/* set PLL3 to new frequency */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_clkgen3_pll
+	la	t1,setting_pll3
+	la	t3,old_pll3
+	lw	t2,0(t0)
+	sw	t2,0(t3)
+	lw	t2,0(t1)
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,0x28000)
+
+	/* Re-attach PLL to MUX */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_sysclk_mux
+	la	t1,setting_mux
+	lw	t2,0(t1)
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,255)
+
+prepare_for_stand_by:
+	/* We enter stand-by mode in local RAM */
+	/* Setup the stack in local RAM */
+	move	t1,sp
+	li	t0,KSEG1_ADDR+REG_BASE_cpu_block
+	addiu	sp,t0,LR_STACKTOP-16 
+	sw	t1,0(sp)
+	sw	ra,4(sp)
+
+	/* Clear BSS */
+	la	t0,_edata
+	la	t1,_end
+2:	beq	t0,t1,3f
+	nop
+
+	sb	zero,0(t0)
+	j	2b
+	addiu	t0,t0,1
+
+3:
+	/* ready to call entry point */
+	DELAY	(t3,t2,255)
+
+#ifdef WITH_INPUT_POLLING
+
+	/* Check do we need to enter standby mode? */
+	beq	a0,zero,not_standby
+	nop
+
+	/* Yes, we do */
+poll_input:
+	move	v0,zero
+	la	a0,ir_keys
+	la	a1,fip_keys
+	la	a2,input_ctrl
+	la	a3,time_elapse
+	jal	polling_input
+	nop
+
+done_poll:
+	la	t0,return_key
+	sw	v0,0(t0)
+
+resume_old_freq:
+	/* set CPU/SYS/DSP to old divider value */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_sysclk_mux
+	la	t1,old_mux
+	lw	t2,0(t1)
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,255)
+
+	/* Detach PLL from MUX, assumed it's been attached before */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_sysclk_mux
+	la	t1,old_mux
+	lw	t2,0(t1)
+	addiu	t2,t2,-1
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,255)
+	/* set PLL3 back to old frequency */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_clkgen3_pll
+	la	t1,old_pll3
+	lw	t2,0(t1)
+	sw	t2,0(t0)
+	sync
+
+	DELAY	(t3,t2,0x28000)
+
+	/* Re-attach PLL from MUX */
+	li	t0,KSEG1_ADDR+REG_BASE_system_block+SYS_sysclk_mux
+	la	t1,old_mux
+	lw	t2,0(t1)
+	sw	t2,0(t0)
+	sync
+
+	/* Restore stack */
+	li	t0,KSEG1_ADDR+REG_BASE_cpu_block
+	addiu	t1,t0,LR_STACKTOP-16
+	lw	sp,0(t1)
+	lw	ra,4(t1)
+
+	b	unset_dram_auto_refresh
+	nop
+
+not_standby:
+
+#else
+	la	t0,return_key
+	la	t1,time_elapse
+	sw	zero,0(t0)
+	sw	zero,0(t1)
+#endif
+
+	move	v0,zero
+
+	/* Restore stack */
+	li	t0,KSEG1_ADDR+REG_BASE_cpu_block
+	addiu	t1,t0,LR_STACKTOP-16 
+	lw	sp,0(t1)
+	lw	ra,4(t1)
+
+	/* reprogram DRAM0/1 configuration */
+	li	t0,KSEG1_ADDR+REG_BASE_dram_controller_0+DRAM_dunit_cfg
+	li	t1,KSEG1_ADDR+REG_BASE_dram_controller_1+DRAM_dunit_cfg
+
+	la	t2,setting_d0cfg
+	lw	t3,0(t2)
+	sw	t3,0(t0)
+	la	t2,setting_d1cfg
+	lw	t3,0(t2)
+	sw	t3,0(t1)
+
+	la	t2,setting_d0delay
+	lw	t3,0(t2)
+	sw	t3,0(t4)
+	la	t2,setting_d1delay
+	lw	t3,0(t2)
+	sw	t3,0(t5)
+	sync
+
+	DELAY	(t3,t2,255)
+
+	b	unset_dram_auto_refresh
+	nop
+
+unset_dram_auto_refresh:
+	/* bring DRAM0/1 out of auto-refresh mode */
+	sw	zero,0(t6)
+	sw	zero,0(t7)
+	sync
+
+	DELAY	(t3,t2,4096)
+
+done:
+	jr	ra
+	nop
+
+END(__frequency_set)
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linux-2.6.15.ref/arch/mips/tangox/fctrl/lib/fc/fip.c linux-2.6.15/arch/mips/tangox/fctrl/lib/fc/fip.c
--- linux-2.6.15.ref/arch/mips/tangox/fctrl/lib/fc/fip.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.6.15/arch/mips/tangox/fctrl/lib/fc/fip.c	2007-07-06 10:25:03.000000000 -0700
@@ -0,0 +1,497 @@
+/*****************************************
+ *  Copyright 漏 2001-2006
+ *  Sigma Designs, Inc. All Rights Reserved
+ *  Proprietary and Confidential
+ ******************************************/
+
+#include <linux/config.h>
+
+#ifdef CONFIG_TANGO2
+#include <asm/tango2/emhwlib_registers_tango2.h>
+#include <asm/tango2/emhwlib_dram_tango2.h>
+#include <asm/tango2/emhwlib_lram.h>
+#elif defined(CONFIG_TANGO3)
+#include <asm/tango3/emhwlib_registers_tango3.h>
+#include <asm/tango3/emhwlib_dram_tango3.h>
+#include <asm/tango2/emhwlib_lram.h>
+#endif
+
+#define KSEG1ADDR(x)            (0xa0000000|(x))
+
+#define __sync()				\
+	__asm__ __volatile__(			\
+		".set	push\n\t"		\
+		".set	noreorder\n\t"		\
+		".set	mips2\n\t"		\
+		"sync\n\t"			\
+		".set	pop"			\
+		: /* no output */		\
+		: /* no input */		\
+		: "memory")
+
+extern void uart_putc(const char c);
+extern void uart_puts(const char *s);
+extern void udelay(unsigned usec);
+
+/* EM86XX */
+#define	FIP_BASE				(REG_BASE_system_block+0x500)
+#define	FIP_COMMAND				0x40
+#define	FIP_DISPLAY_DATA			0x44
+#define	FIP_LED_DATA				0x48
+#define	FIP_KEY_DATA1				0x4c
+#define	FIP_KEY_DATA2				0x50
+#define	FIP_SWITCH_DATA				0x54
+#define FIP_CONFIG				0x58
+#define FIP_INT					0x5c