1000.tango2.patch

sm86xx内核源包括补丁（ GPL ）的

+unsigned int xenv_scard_5v_pin = 0, xenv_scard_off_pin = 0, xenv_scard_cmd_pin = 0;
+unsigned int xenv_cs_flash_size[4] = { 0, 0, 0, 0 };
+unsigned int xenv_cs_flash_parts[4] = { 0, 0, 0, 0 };
+unsigned int xenv_flash_parts_size[4][XENV_MAX_FLASH_PARTITIONS];
+unsigned int xenv_flash_parts_offset[4][XENV_MAX_FLASH_PARTITIONS];
+unsigned int xenv_uart_console_port = 0;
+unsigned int xenv_uart_used_ports = 1;
+
+static unsigned int xenv_enabled_devices = 0;
+static unsigned int xenv_isaide_timing_slot = 0;
+static unsigned int xenv_isaide_irq = 0;
+static unsigned int xenv_mac_hi = 0, xenv_mac_lo = 0;
+static unsigned int xenv_pcidev_irq_route[4] = { 0, 0, 0, 0 };
+
+static unsigned long xenv_addr = 0, xenv_gbus_addr = 0;
+
+#define ISAIDE_SHIFT		0
+#define BMIDE_SHIFT		1
+#define PCIHOST_SHIFT		2
+#define ETHERNET_SHIFT		3
+#define IR_SHIFT		4
+#define FIP_SHIFT		5	
+#define I2CM_SHIFT		6
+#define I2CS_SHIFT		7
+#define SDIO_SHIFT		8
+#define USB_SHIFT		9
+#define PCI1_SHIFT		10
+#define PCI2_SHIFT		11
+#define PCI3_SHIFT		12
+#define PCI4_SHIFT		13
+#define PCI5_SHIFT		14
+#define PCI6_SHIFT		15
+#define SATA_SHIFT		16
+#define SCARD_SHIFT		17
+#define GNET_SHIFT		18
+/*				19-32: undefined */
+#else
+/* !CONFIG_TANGO2_SIG_BLOCK && !CONFIG_TANGO2_XENV */
+#endif
+
+#if defined(CONFIG_TANGO2_SIG_BLOCK) || defined(CONFIG_TANGO2_XENV)
+static int tango2_device_info(void);
+unsigned long em8xxx_baudrates[2] = { CONFIG_TANGO2_BASE_BAUD, CONFIG_TANGO2_BASE_BAUD };
+#else
+/* !CONFIG_TANGO2_SIG_BLOCK && !CONFIG_TANGO2_XENV */
+#endif
+
+#ifdef CONFIG_TANGO2_USE_TLB_REMAP_DRAM1 
+unsigned long em86xx_tlb_dram1_map_base = 0L;
+unsigned long em86xx_tlb_dram1_map_size = 0L;
+#endif
+
+const char *get_system_type(void)
+{
+	return "SigmaDesigns Tango2";
+}
+
+unsigned long tango2_get_sysclock(void)
+{
+#if (EM86XX_REVISION > 3)
+	unsigned long sys_clkgen_pll, sysclk_mux, sysclk_premux, n, m, freq, div, k, mux;
+
+	k = m = sys_clkgen_pll = 0;
+ 	sysclk_mux = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_sysclk_mux);
+ 	sysclk_premux = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_sysclk_premux);
+	switch(sysclk_premux & 0x3) {
+		case 0:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen0_pll);
+			m = (sys_clkgen_pll >> 16) & 0x1f;
+			k = (sys_clkgen_pll >> 14) & 0x3;
+			break;
+		case 1:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen1_pll);
+			m = (sys_clkgen_pll >> 16) & 0x7f;
+			break;
+		case 2:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen2_pll);
+			m = (sys_clkgen_pll >> 16) & 0x7f;
+			break;
+		case 3:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen3_pll);
+			m = (sys_clkgen_pll >> 16) & 0x7f;
+			break;
+	}
+        n = sys_clkgen_pll & 0x000003ff;
+
+	/* Not using XTAL_IN, cannot calculate */
+	if ((sys_clkgen_pll & 0x07000000) != 0x01000000)
+		return(0);
+
+	/* Calculate the divider */
+	mux = (sysclk_mux >> 8) & 0xf;
+	if (mux == 0) /* Get system clock frequency */
+		div = 2;
+	else if ((mux == 1) || ((mux >= 8) && (mux < 0xc)))
+		div = 4;
+	else if ((mux >= 2) && (mux < 8))
+		div = 3;
+	else
+		return(0); /* Wrong divider setting */
+
+	if (sysclk_mux & 0x1) 	/* PLL is used */
+		freq = ((TANGO2_BASE_FREQUENCY / (m + 2)) * (n + 2)) / (div * (1 << k));
+	else
+		freq = TANGO2_BASE_FREQUENCY / div;
+#else
+	unsigned long sys_clkgen_pll, sysclk_mux, n, m, freq, div;
+ 	sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen_pll);
+ 	sysclk_mux = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_sysclk_mux);
+        n = sys_clkgen_pll & 0x000003ff;
+        m = (sys_clkgen_pll & 0x003f0000) >> 16;
+
+	/* Calculate the divider */
+	if ((sysclk_mux & 0x300) == 0x000) /* Get system clock frequency */
+		div = 2;
+	else if ((sysclk_mux & 0x300) == 0x100)
+		div = 4;
+	else
+		div = 3;
+
+	if (sysclk_mux & 0x1) 	/* PLL is used */
+		freq = ((TANGO2_BASE_FREQUENCY / (m + 2)) * (n + 2)) / div;
+	else
+		freq = TANGO2_BASE_FREQUENCY / div;
+#endif
+	return(freq);
+}
+
+unsigned long tango2_get_cpuclock(void)
+{
+#if (EM86XX_REVISION > 3)
+	unsigned long sys_clkgen_pll, sysclk_mux, sysclk_premux, n, m, freq, div, k, mux;
+
+	k = m = sys_clkgen_pll = 0;
+ 	sysclk_mux = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_sysclk_mux);
+ 	sysclk_premux = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_sysclk_premux);
+	switch(sysclk_premux & 0x3) {
+		case 0:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen0_pll);
+			m = (sys_clkgen_pll >> 16) & 0x1f;
+			k = (sys_clkgen_pll >> 14) & 0x3;
+			break;
+		case 1:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen1_pll);
+			m = (sys_clkgen_pll >> 16) & 0x7f;
+			break;
+		case 2:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen2_pll);
+			m = (sys_clkgen_pll >> 16) & 0x7f;
+			break;
+		case 3:
+			sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen3_pll);
+			m = (sys_clkgen_pll >> 16) & 0x7f;
+			break;
+	}
+        n = sys_clkgen_pll & 0x000003ff;
+
+	/* Not using XTAL_IN, cannot calculate */
+	if ((sys_clkgen_pll & 0x07000000) != 0x01000000)
+		return(0);
+
+	/* Calculate the divider */
+	mux = (sysclk_mux >> 8) & 0xf;
+	if ((mux == 3) || (mux == 4) || (mux == 6)) /* Get CPU frequency */
+		div = 3;
+	else if ((mux == 8) || (mux == 0xa))
+		div = 4;
+	else if ((mux == 0) || (mux == 1) || (mux == 2) || (mux == 5) || (mux == 7) || 
+			(mux == 9) || (mux == 0xb))
+		div = 2;
+	else
+		return(0); /* Wrong divider setting */
+
+	if (sysclk_mux & 0x1) 	/* PLL is used */
+		freq = ((TANGO2_BASE_FREQUENCY / (m + 2)) * (n + 2)) / (div * (1 << k));
+	else
+		freq = TANGO2_BASE_FREQUENCY / div;
+#else
+	unsigned long sys_clkgen_pll, sysclk_mux, n, m, freq, div;
+ 	sys_clkgen_pll = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_clkgen_pll);
+ 	sysclk_mux = *(volatile unsigned long *)KSEG1ADDR(REG_BASE_system_block + SYS_sysclk_mux);
+        n = sys_clkgen_pll & 0x000003ff;
+        m = (sys_clkgen_pll & 0x003f0000) >> 16;
+
+	if ((sysclk_mux & 0x300) == 0x300) /* Get CPU frequency */
+		div = 3;
+	else
+		div = 2;
+
+	/* Calculate the divider */
+	if (sysclk_mux & 0x1) 	/* PLL is used */
+		freq = ((TANGO2_BASE_FREQUENCY / (m + 2)) * (n + 2)) / div;
+	else
+		freq = TANGO2_BASE_FREQUENCY / div;
+#endif
+	return(freq);
+}
+
+#if 0
+// rather do this from gdb with jtag [hwb_rw gdb macro]
+
+/// 
+/**
+   <long-description>
+
+   @param start 
+   @param size  power of two bw 8 and 4096
+   @param mode  1:W 2:R 4:I
+*/
+void setup_watch(unsigned long start,int size,int mode)
+{
+	start=start&(~7);
+
+	emprintk("watching mode %d [%p,%p]\n",mode,start,start+size);
+	write_c0_watchlo0(start|mode);
+	write_c0_watchhi0((1<<30)|((size-1)&(~7)));
+}
+#endif
+
+void kernel_entry(void);
+
+int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
+{
+	extern char _ftext; /* For code start address (not entry address)  */
+	unsigned long kend;
+	unsigned long offset;
+	memcfg_t *m=(memcfg_t *)KSEG1ADDR(MEM_BASE_dram_controller_0+FM_MEMCFG);
+	int i;
+
+#ifdef CONFIG_CMDLINE_BOOL
+	strcpy (arcs_cmdline, CONFIG_CMDLINE);
+#endif
+
+#if defined(CONFIG_TANGO2_SIG_BLOCK)
+	/* Save the signature block locally */
+	memcpy(&sigblock, (struct signature_block *)KSEG1ADDR(0x1fc00000), sizeof(struct signature_block));
+	sigptr = &sigblock;
+
+	/* Get the baudrate information from signature block */
+	if ((em8xxx_baudrates[0] = em8xxx_baudrates[1] = zboot_default_baudrate(sigptr)) == 0) 
+		em8xxx_baudrates[0] = em8xxx_baudrates[1] = CONFIG_TANGO2_BASE_BAUD; /* Use default */
+#elif defined(CONFIG_TANGO2_XENV)
+	if ((xenv_gbus_addr = xenv_addr = gbus_read_uint32(pGBus, REG_BASE_cpu_block + LR_XENV_LOCATION)) != 0) {
+		/* Got the xenv address in gbus form, now convert it in remap from so we can access it */
+		gbus_write_uint32(pGBus, REG_BASE_cpu_block + REMAPPED_REG, xenv_addr & 0xfc000000);
+		iob();
+		xenv_addr = REMAPPED_BASE + (xenv_addr & 0x03ffffff);
+
+		if (xenv_isvalid((void *)xenv_addr, MAX_XENV_SIZE) < 0)
+			xenv_addr = 0;
+	}
+
+	if (xenv_addr == 0) 
+		printk("WARNING: Cannot found valid XENV block.\n");
+	else {
+		extern int tango2_pcidev_enabled(const int pci_idsel);
+		unsigned long cs_config = (gbus_read_uint32(pGBus, REG_BASE_host_interface + PB_CS_config) >> 12) & 0xf;
+		unsigned int val;
+		RMuint32 size;
+		char buf[32], xenv_cmdline[CL_SIZE];
+		int j;
+
+		memset(&xenv_flash_parts_size[0][0], 0, sizeof(xenv_flash_parts_size));
+		memset(&xenv_flash_parts_offset[0][0], 0, sizeof(xenv_flash_parts_offset));
+
+		/* Getting Linux command line from XENV */
+		size = CL_SIZE;
+		if (xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_LINUX_CMD, xenv_cmdline, &size) == RM_OK) {
+			xenv_cmdline[size] = '\0';
+			if (xenv_cmdline[0] == '\"') {
+				if (xenv_cmdline[size -1] == '\"')
+					xenv_cmdline[size - 1] = '\0';
+				strcpy(arcs_cmdline, &xenv_cmdline[1]);
+			} else
+				strcpy(arcs_cmdline, &xenv_cmdline[0]);
+		}
+
+		size = 4;
+		if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_DEF_BAUDRATE, &val, &size) == RM_OK) && (size == 4))
+			em8xxx_baudrates[0] = em8xxx_baudrates[1] = val;
+		size = 4;
+		if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_ENABLED_DEVICES, &val, &size) == RM_OK) && (size == 4)) 
+			xenv_enabled_devices = val;
+		size = 4;
+		if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_ISAIDE_IRQ_ROUTE, &val, &size) == RM_OK) && (size == 4)) 
+			xenv_isaide_irq = (int)(val & 0x3);
+		size = 4;
+	        if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_ISAIDE_TIMING_SLOT, &val, &size) == RM_OK) && (size == 4))
+			xenv_isaide_timing_slot = (int)(val & 0x7);
+		size = 4;
+	        if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_SCARD_OFF, &val, &size) == RM_OK) && (size == 4))
+			xenv_scard_off_pin = val;
+		size = 4;
+	        if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_SCARD_5V, &val, &size) == RM_OK) && (size == 4))
+			xenv_scard_5v_pin = val;
+		size = 4;
+	        if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_SCARD_CMD, &val, &size) == RM_OK) && (size == 4))
+			xenv_scard_cmd_pin = val;
+		size = 4;
+	        if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_CONSOLE_UART_PORT, &val, &size) == RM_OK) && (size == 4))
+			xenv_uart_console_port = val;
+		size = 4;
+	        if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, XENV_KEY_UART_USED_PORTS, &val, &size) == RM_OK) && (size == 4))
+			xenv_uart_used_ports = val;
+
+		if (xenv_uart_console_port == 0) /* for backward compatibility */
+			xenv_uart_used_ports |= 1;
+
+		for (i = 0; i < 2; i++) {
+			sprintf(buf, XENV_KEYS_UART_BAUDRATE, i);
+			size = 4;
+			if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, buf, &val, &size) == RM_OK) && (size == 4))
+				em8xxx_baudrates[i] = val;
+		}
+
+		/* Boot program (e.g. zboot) should set up this already. */
+		xenv_mac_hi = gbus_read_uint32(pGBus, REG_BASE_cpu_block + LR_ETH_MAC_HI) & 0xffff;
+		xenv_mac_lo = gbus_read_uint32(pGBus, REG_BASE_cpu_block + LR_ETH_MAC_LO);
+
+		// Getting PCI IRQ routing information
+		for (i = 1; i <= 4; i++) {
+			if (!tango2_pcidev_enabled(i))
+				continue;
+			sprintf(buf, XENV_KEYS_PCI_IRQ_ROUTE, i);
+	                size = 4;
+	                if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, buf, &val, &size) == RM_OK) && (size == 4)) 
+				xenv_pcidev_irq_route[i - 1] = val;
+		}
+		/* Save all cs0-cs3 flash keys needed from XENV */
+		for (i = 0; i < 4; i++) {
+			if ((cs_config & (1 << i)) != 0) /* Check to see if see to IDE mode */
+				continue;
+			sprintf(buf, XENV_KEYS_CS_SIZE, i);
+			size = 4;
+			if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, buf, &val, &size) == RM_OK) && (size == 4)) 
+				xenv_cs_flash_size[i] = val;
+			if (xenv_cs_flash_size[i] == 0)
+				continue;
+			sprintf(buf, XENV_KEYS_CS_PARTS, i);
+			size = 4;
+			if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, buf, &val, &size) == RM_OK) && (size == 4)) {
+				xenv_cs_flash_parts[i] = val;
+				for (j = 0; j < xenv_cs_flash_parts[i]; j++) {
+					sprintf(buf, XENV_KEYS_CS_PART_SIZE, i, j + 1);
+					size = 4;
+					if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, buf, &val, &size) == RM_OK) && (size == 4)) 
+						xenv_flash_parts_size[i][j] = val;
+					sprintf(buf, XENV_KEYS_CS_PART_OFFSET, i, j + 1);
+					size = 4;
+					if ((xenv_get((void *)xenv_addr, MAX_XENV_SIZE, buf, &val, &size) == RM_OK) && (size == 4)) 
+						xenv_flash_parts_offset[i][j] = val;
+				}
+			}
+		}
+	}
+#endif
+
+	/* Pass argument in ordinary way, override the command line */
+	if ((argc > 1) && (argc < 65) && (argv != NULL)) { /* Up to 64 arguments */
+		arcs_cmdline[0] = '\0';
+		for (i = 1; i < argc; i++) {
+			strcat(arcs_cmdline, argv[i]);
+			strcat(arcs_cmdline, " ");
+		}
+	}
+
+	em8xxx_kmem_start = ((unsigned long)(&_ftext) & 0xfffff000); /* Aligned by 4KB */
+	/* Aligned by MB boundary */
+	em8xxx_kmem_size = ((em8xxx_kmem_start + TANGO2_SYSTEMRAM_ACTUALSIZE) & 0xfff00000) - em8xxx_kmem_start;
+ 
+	/* Re-program CPU_remap so we can see full 256MB space in KSEG0/KSEG1 */
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_remap, 0x1fc00000);
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_remap1, 0x00000000);
+	iob();
+
+#ifdef CONFIG_UART_USE_SYSCLK
+ 	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_UART0_base + CPU_UART_CLKSEL, 0);
+ 	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_UART1_base + CPU_UART_CLKSEL, 0);
+#else
+ 	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_UART0_base + CPU_UART_CLKSEL, 1);
+ 	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_UART1_base + CPU_UART_CLKSEL, 1);
+#endif
+
+	/* you should these macros defined in include/asm/bootinfo.h */
+        mips_machgroup = MACH_GROUP_SIGMADESIGNS;
+        mips_machtype = MACH_TANGO2;
+	__write_32bit_c0_register($15, 1, kernel_entry);
+
+	kend = KSEG1ADDR(em8xxx_kmem_start + em8xxx_kmem_size) - KSEG1ADDR(MEM_BASE_dram_controller_0);
+
+	if (is_valid_memcfg(m) == 0) {
+		memset(m,0,sizeof(memcfg_t));
+		m->signature=MEMCFG_SIGNATURE;
+		m->dram0_size=TANGO2_SYSTEMRAM_ACTUALSIZE;
+		m->kernel_end=kend;
+		gen_memcfg_checksum(m);
+//		emprintk("ebase @%08lx. memcfg ready @%08lx.\n", read_c0_ebase(), MEM_BASE_dram_controller_0+FM_MEMCFG);
+	} else {