1010.pci.patch

sm86xx内核源包括补丁（ GPL ）的

+	gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_chip_is_host, 1);
+
+    // HOST_REG1 :
+    //   [31:16] : # of PCI retry cycle = 0xffff (default = 0xff)
+    //   [8] : host Super Request = 0
+    //   [3:0] arbitration level = 0x00 (Level 1)
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_host_reg1,
+		0xffff0000 | PCIEM86XX_ARBITER_LEVEL);
+
+    // PCI_CTRL1 :
+    //   [17] : enable "Memory Read Multiple" and "Memory Read Line"
+    //   [16] [7:0] : enable "prefetch" for PCI slave regions 2..7
+    //   [17] : Always enabled
+    //   [18] : additional bit for Tango. Long PCI memory read burst
+//	gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_pcictrl_reg1, 0x000700fc);
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_pcictrl_reg1, 0x00030000);
+
+    // PCI_CTRL2 :
+    //   [18] : fast back-to-back capable = 0 (default)
+    //   [17] : read FIFO level = 1 (8 level deep, default)
+    //   [16] : discard timer enable = 1 (default)
+    //   [15:8] : subs latency = 0x06 (default = 0x08)
+    //   [7:0] : initial latency = 0x0d (default = 0x0b)
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_pcictrl_reg2, 0x0003060d);
+
+    // PCI_CTRL3 :
+    //   [16] : slave abort clear = 0
+    //   [10:8] : abort interrupt enable = 0 (default)
+    //   [2:0] : abort status = 0
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_pcictrl_reg3, 0);
+
+    // clear PCI bus fault
+    if (((gbus_read_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 3) >> 1) & 0x3) != 0) {
+	gbus_write_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 3, 1);
+	gbus_write_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 3, 0);
+    }
+
+    // Setting pci_configuration_vld 
+    gbus_write_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 2, 1);
+
+    // grant timeout
+    gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_host_reg3, PCIEM86XX_ARBITER_GRANTTIMEOUT);
+    gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_host_reg5, PCIEM86XX_ARBITER_GRANTTIMEOUT & 0x000000ff);
+                                                                                
+    // initialize arbiter
+    gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_host_reg4, 0);
+
+    // detect each agent
+    memset(&g_idsel_func_exist[0], 0, sizeof(int) * PCIEM86XX_IDSEL_MAX * 8);
+
+    /* Briefly scanning the bus for devices */
+    for (idsel = 1; idsel < PCIEM86XX_IDSEL_MAX; ++idsel) {
+        for (i = 1; i <= 3; ++i) {
+            if ((pciid = tango2_pci_select(idsel)) != 0)
+                break;
+        }
+#if defined(CONFIG_TANGO2_SIG_BLOCK) || defined(CONFIG_TANGO2_XENV)
+    	if (tango2_pcidev_enabled(idsel) == 0)
+      	    g_idsel_exist[idsel] = pciid = 0;
+	else
+            g_idsel_exist[idsel] = (pciid == 0) ? 0 : 1;
+#else
+        g_idsel_exist[idsel] = (pciid == 0) ? 0 : 1;
+#endif
+	if (pciid != 0) {
+	    printk("PCI: found device IDSEL = %d\n", idsel);
+	    for (i = idsel * 8; i < (idsel + 1) * 8; i++)
+		g_idsel_func_exist[i] = 1;
+	}
+    }
+
+    // Initialize IDSEL 0 - EM86XX as a PCI slave
+    for (i = 1; i <= 3; ++i) {
+        if ((pciid = tango2_pci_select(0)) != 0)
+            break;
+        printk("PCI: Probing EM86XX at IDSEL 0, retry = %d\n", i);
+    }
+
+    if (pciid == 0) {
+        printk("PCI: Can't initialize EM86XX as a PCI slave\n");
+	goto pci_init_end;
+    } else {
+        /* Start configuring memory spaces .. */
+        unsigned long memsize, regsize, membase;
+
+	g_pcimem_phyaddr = PHYSADDR(em8xxx_kmem_start);
+
+        // set PCI memory size to maximum, so the PCI memory will cover the
+        // whole memory if the total DRAM size is smaller than 112MB.
+        // maximum = 128MB => 16MB per region => DMA memory = 16 * 7 = 112MB
+        // But the current code doesn't care 2nd DRAM controller.
+        gbus_write_uint8(pGBus, REG_BASE_host_interface + PCI_REG3, 0x7);
+                                                                                
+        memsize = gbus_read_uint32(pGBus, REG_BASE_host_interface + PCI_REG3) & 0x07;
+        memsize = 1 << memsize;
+        regsize = (memsize << 20) >> 3; // memory size / 8
+
+        // pci command
+        __raw_writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, tango2_pci_config_base + PCI_COMMAND);
+
+        // base address 0
+        __raw_writel(g_pcimem_busaddr, tango2_pci_config_base + PCI_BASE_ADDRESS_0);
+                                                                                
+        // PCI slave access
+        // region 0 (R) : Configuration area
+        // region 1 - 7: mapped to DRAM starting from DRAM_BASE
+        g_pcimem_busaddr += (regsize * 1);
+        printk("PCI: Configured SMP863x as PCI slave with %dMB PCI memory\n", memsize);
+        membase = PHYSADDR(em8xxx_kmem_start);
+        g_pcimem_phyaddr = membase;
+        g_pcimem_phyaddr_end = g_pcimem_phyaddr + em8xxx_kmem_size;
+        for (i = 1; i < 8; ++i) {
+            // PCI region base registers should contain low address
+            gbus_write_uint32(pGBus, REG_BASE_host_interface + PCI_REGION_0_BASE + (i * 4), PHYSADDR(membase));
+            membase += regsize;
+        }
+        if (g_pcimem_phyaddr_end > membase)
+            g_pcimem_phyaddr_end = membase;
+        printk("PCI: Region size is %dKB\n", regsize >> 10);
+        printk("PCI: Map DMA memory 0x%08x-0x%08x for PCI at 0x%08x\n",
+            g_pcimem_phyaddr, g_pcimem_phyaddr_end, g_pcimem_busaddr);
+    }
+
+pci_init_end:
+
+    return(0);
+}
+
+static void tango2_pci_busfault_intr(int irq, void *devinfo, struct pt_regs *regs)
+{
+    static char *s_fault_reason[] = {
+        "OK", "Master Abort", "Retry timer expired", "Unknown" };
+                                                                                
+    static int s_faultcount = 0;
+    unsigned int data;
+                                                                                
+    data = (gbus_read_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 3) >> 1) & 3;
+                                                                                
+    if (data == 1) {
+        printk("GPF: pid(%d, <%s>), EPC=0x%08lx\n", current->pid, current->comm, regs->cp0_epc);
+    } else
+        printk("PCI: PCI bus fault (%d): %s", ++s_faultcount, s_fault_reason[data]);
+
+    // clears PCI bus fault flags
+    gbus_write_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 3, 1);
+    gbus_write_uint8(pGBus, REG_BASE_host_interface + PCI_host_reg2 + 3, 0);
+}
+
+void __init tango2_pcibios_init(void)
+{
+#if defined(CONFIG_TANGO2_SIG_BLOCK) || defined(CONFIG_TANGO2_XENV)
+	if (tango2_pci_host_enabled() == 0)
+		return;
+#endif
+
+	tango2_pci_config_base = (unsigned long)ioremap(MEMORY_BASE_PCI_CONFIG, PCIEM86XX_IDSEL_MAX * 0x800);
+	tango2_pci_io_base = (unsigned long)ioremap(MEMORY_BASE_PCI_IO, 0x08000000);
+//	tango2_pci_mem_base = (unsigned long)ioremap(MEMORY_BASE_PCI_MEMORY, 0x10000000); /* should be 0x20000000 */
+
+	printk("Remapping PCI config space 0x%08lx to 0x%08lx, size 0x%x\n", 
+		MEMORY_BASE_PCI_CONFIG, tango2_pci_config_base, PCIEM86XX_IDSEL_MAX * 0x800);
+	printk("Remapping PCI I/O space 0x%08lx to 0x%08lx, size 0x%x\n", 
+		MEMORY_BASE_PCI_IO, tango2_pci_io_base, 0x08000000);
+//	printk("Remapping PCI memory space 0x%08lx to 0x%08lx, size 0x%x\n", 
+//		MEMORY_BASE_PCI_MEMORY, tango2_pci_mem_base, 0x10000000);
+
+	/* The base address for MIPS I/O port, which will be used by
+	   I/O functions such like inb(), outb(), ...  */
+	set_io_port_base(tango2_pci_io_base);
+
+	tango2_pci_init();
+
+        request_irq(LOG2_CPU_PCI_FAULT_INT + IRQ_CONTROLLER_IRQ_BASE, tango2_pci_busfault_intr, SA_SHIRQ, "TANGO2 PCI HOST", tango2_pci_busfault_intr);
+}
+
+unsigned long tango2_virt_to_bus(unsigned long virt_addr)
+{
+    if ((PHYSADDR(virt_addr) < g_pcimem_phyaddr) || (PHYSADDR(virt_addr) >= g_pcimem_phyaddr_end))
+	printk("virt2bus: Not a dma-able address: 0x%08x\n", virt_addr); 
+    return((unsigned long)(PHYSADDR(virt_addr)-g_pcimem_phyaddr+g_pcimem_busaddr));
+}
+
+unsigned long tango2_bus_to_virt(unsigned long bus_addr)
+{
+    if ((bus_addr < g_pcimem_busaddr) || (bus_addr >= (g_pcimem_busaddr + (g_pcimem_phyaddr_end - g_pcimem_phyaddr)))) 
+	printk("bus2virt: Not a valid bus address: 0x%08x\n", bus_addr);
+    return((unsigned long)(bus_addr-g_pcimem_busaddr+g_pcimem_phyaddr));
+}
+
+EXPORT_SYMBOL(tango2_virt_to_bus);
+EXPORT_SYMBOL(tango2_bus_to_virt);
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/arch/mips/tango2/pci_fixups.c linuxmips-2.4.30/arch/mips/tango2/pci_fixups.c
--- linuxmips-2.4.30.ref/arch/mips/tango2/pci_fixups.c	1969-12-31 16:00:00.000000000 -0800
+++ linuxmips-2.4.30/arch/mips/tango2/pci_fixups.c	2007-01-09 13:01:43.000000000 -0800
@@ -0,0 +1,70 @@
+
+/*****************************************
+ Copyright 漏 2001-2003  
+ Sigma Designs, Inc. All Rights Reserved
+ Proprietary and Confidential
+ *****************************************/
+/**
+  @file   pci_fixups.c
+  @brief  
+
+  PCI support (fixups) for Tango2.
+
+  @author YH Lin
+  @date   2005-01-20
+*/
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci_ids.h>
+
+#include <asm/tango2/rmdefs.h>
+#include <asm/tango2/hardware.h>
+
+#if defined(CONFIG_TANGO2_SIG_BLOCK) || defined(CONFIG_TANGO2_XENV)
+extern int tango2_pcidev_irq_map(const int pci_idsel, const int int_num);
+#endif
+
+extern unsigned short get_gt_devid(void);
+
+void __init pcibios_fixup_resources(struct pci_dev *dev)
+{
+}
+
+void __init pcibios_fixup(void)
+{
+}
+
+void __init pcibios_fixup_irqs(void)
+{
+	struct pci_dev *dev;
+
+	pci_for_each_dev(dev) {
+		if (dev->bus->number != 0)
+			return;
+		else {
+#if defined(CONFIG_TANGO2_SIG_BLOCK) || defined(CONFIG_TANGO2_XENV)
+			unsigned int slot = PCI_SLOT(dev->devfn);
+			unsigned char irqpin;
+
+			pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irqpin);
+			if (irqpin) { /* This device is using interrupt */
+				dev->irq = tango2_pcidev_irq_map(slot, irqpin - 1);
+				pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+			}
+#else
+			/* for generic */
+			dev->irq = IRQ_PCI;
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+#endif
+		}
+	}
+}
+
+unsigned int pcibios_assign_all_busses(void)
+{
+	return 0;
+}
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/arch/mips/tango2/setup.c linuxmips-2.4.30/arch/mips/tango2/setup.c
--- linuxmips-2.4.30.ref/arch/mips/tango2/setup.c	2007-01-09 12:56:44.000000000 -0800
+++ linuxmips-2.4.30/arch/mips/tango2/setup.c	2007-01-09 13:01:43.000000000 -0800
@@ -35,6 +35,7 @@
 #include <asm/tango2/rmdefs.h>
 
 extern int em86xx_sbox_init(void);
+extern void pci_disable_device_all(void);
  
 void tango2_restart(char *command)
 {
@@ -46,6 +47,11 @@
 	/* Disable timer */
 	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_time0_ctrl, 0);
 #endif
+#ifdef CONFIG_PCI
+	/* Disable all pci devices,
+	 * for reboot problem after loading usb drivers*/
+	pci_disable_device_all();
+#endif
 
 #if (EM86XX_REVISION > 3)
         /* Resetting Tango2 EHCI */
@@ -236,6 +242,10 @@
                                                                                  
  	// use GPIO#8, IRQ 14 for PCI IRQ, ISA IDE uses GPIO#6.
  	gbus_write_uint32(pGBus, REG_BASE_system_block + SYS_gpio_int, 0x0607080d);
+ 
+	// Set the PCI IRQ to be active low, level triggered
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_edge_config_rise_set, 1 << LOG2_CPU_PCI_INTB);
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_edge_config_fall_set, 1 << LOG2_CPU_PCI_INTB);
 #endif
 }
 
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/drivers/pci/pci.c linuxmips-2.4.30/drivers/pci/pci.c
--- linuxmips-2.4.30.ref/drivers/pci/pci.c	2004-11-18 16:28:41.000000000 -0800
+++ linuxmips-2.4.30/drivers/pci/pci.c	2007-01-09 13:01:43.000000000 -0800
@@ -28,6 +28,10 @@
 #include <asm/page.h>
 #include <asm/dma.h>	/* isa_dma_bridge_buggy */
 
+#ifdef CONFIG_TANGO2
+#include <asm/tango2/hardware.h>
+#endif
+
 #undef DEBUG
 
 #ifdef DEBUG
@@ -36,6 +40,8 @@
 #define DBG(x...)
 #endif
 
+int pci_enabled = 1; /* By default it's enabled */
+
 LIST_HEAD(pci_root_buses);
 LIST_HEAD(pci_devices);
 
@@ -1077,12 +1083,18 @@
 		if (l == 0xffffffff)
 			l = 0;
 		if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {