1005.sbox-mbus-gpio.patch

sm86xx内核源包括补丁（ GPL ）的

+int em86xx_gpio_read(int gpio)
+{
+#if (EM86XX_REVISION > 3)
+	if ((gpio >= 0) && (gpio < 16))
+		return (gbus_read_uint32(pGBus, REG_BASE_system_block + SYS_gpio_data) >> gpio) & 1;
+	else /* Upper 16 */
+		return (gbus_read_uint32(pGBus, REG_BASE_host_interface + ETH_gpio_data2) >> (gpio - 16)) & 1;
+#else
+	return (gbus_read_uint32(pGBus, REG_BASE_system_block + SYS_gpio_data) >> gpio) & 1;
+#endif
+}
+
+void em86xx_gpio_write(int gpio, int data)
+{
+#if (EM86XX_REVISION > 3)
+	if ((gpio >= 0) && (gpio < 16))
+		gbus_write_uint32(pGBus, REG_BASE_system_block + SYS_gpio_data,
+				data ? GPIO_DATA_SET(gpio) : GPIO_DATA_CLEAR(gpio));
+	else /* Upper 16 */
+		gbus_write_uint32(pGBus, REG_BASE_host_interface + ETH_gpio_data2,
+				data ? GPIO_DATA_SET(gpio - 16) : GPIO_DATA_CLEAR(gpio - 16));
+#else
+	gbus_write_uint32(pGBus, REG_BASE_system_block + SYS_gpio_data,
+		data ? GPIO_DATA_SET(gpio) : GPIO_DATA_CLEAR(gpio));
+#endif
+}
+
+void em86xx_gpio_setdirection(int gpio, int dir)
+{
+#if (EM86XX_REVISION > 3)
+	if ((gpio >= 0) && (gpio < 16))
+		gbus_write_uint32(pGBus, REG_BASE_system_block + SYS_gpio_dir,
+				dir ? GPIO_DIR_OUTPUT(gpio) : GPIO_DIR_INPUT(gpio));
+	else /* Upper 16 */
+		gbus_write_uint32(pGBus, REG_BASE_host_interface + ETH_gpio_dir2,
+				dir ? GPIO_DIR_OUTPUT(gpio - 16) : GPIO_DIR_INPUT(gpio - 16));
+#else
+	gbus_write_uint32(pGBus, REG_BASE_system_block + SYS_gpio_dir,
+		dir ? GPIO_DIR_OUTPUT(gpio) : GPIO_DIR_INPUT(gpio));
+#endif
+}
+
+#if defined(CONFIG_TANGO2_UART0_AS_GPIO_FULL) || defined(CONFIG_TANGO2_UART0_AS_GPIO_PARTIAL) || defined(CONFIG_TANGO2_XENV)
+int em86xx_uart0_gpio_read(int gpio)
+{
+	return (gbus_read_uint16(pGBus, REG_BASE_cpu_block + CPU_uart0_gpio_data) >> gpio) & 1;
+}
+
+void em86xx_uart0_gpio_write(int gpio, int data)
+{
+	gbus_write_uint16(pGBus, REG_BASE_cpu_block + CPU_uart0_gpio_data,
+		data ? UART_GPIO_DATA_SET(gpio) : UART_GPIO_DATA_CLEAR(gpio));
+}
+
+void em86xx_uart0_gpio_setdirection(int gpio, int dir)
+{
+	gbus_write_uint16(pGBus, REG_BASE_cpu_block + CPU_uart0_gpio_dir, 
+		dir ? UART_GPIO_DIR_OUTPUT(gpio) : UART_GPIO_DIR_INPUT(gpio));
+}
+#endif
+
+#if defined(CONFIG_TANGO2_UART1_AS_GPIO_FULL) || defined(CONFIG_TANGO2_UART1_AS_GPIO_PARTIAL) || defined(CONFIG_TANGO2_XENV)
+int em86xx_uart1_gpio_read(int gpio)
+{
+	return (gbus_read_uint16(pGBus, REG_BASE_cpu_block + CPU_uart1_gpio_data) >> gpio) & 1;
+}
+
+void em86xx_uart1_gpio_write(int gpio, int data)
+{
+	gbus_write_uint16(pGBus, REG_BASE_cpu_block + CPU_uart1_gpio_data, 
+		data ? UART_GPIO_DATA_SET(gpio) : UART_GPIO_DATA_CLEAR(gpio));
+}
+
+void em86xx_uart1_gpio_setdirection(int gpio, int dir)
+{
+	gbus_write_uint16(pGBus, REG_BASE_cpu_block + CPU_uart1_gpio_dir, 
+		dir ? UART_GPIO_DIR_OUTPUT(gpio) : UART_GPIO_DIR_INPUT(gpio));
+}
+#endif
+
+EXPORT_SYMBOL(mbus_memcpy);
+EXPORT_SYMBOL(em86xx_mbus_wait);
+EXPORT_SYMBOL(em86xx_mbus_reset);
+EXPORT_SYMBOL(em86xx_mbus_free_dma);
+EXPORT_SYMBOL(em86xx_mbus_setup_dma);
+EXPORT_SYMBOL(em86xx_mbus_alloc_dma);
+EXPORT_SYMBOL(em86xx_mbus_setup_dma_linear);
+EXPORT_SYMBOL(em86xx_mbus_setup_dma_double);
+EXPORT_SYMBOL(em86xx_mbus_setup_dma_rectangle);
+EXPORT_SYMBOL(em86xx_gpio_read);
+EXPORT_SYMBOL(em86xx_gpio_write);
+EXPORT_SYMBOL(em86xx_gpio_setdirection);
+
+#if defined(CONFIG_TANGO2_UART0_AS_GPIO_FULL) || defined(CONFIG_TANGO2_UART0_AS_GPIO_PARTIAL) || defined(CONFIG_TANGO2_XENV)
+EXPORT_SYMBOL(em86xx_uart0_gpio_read);
+EXPORT_SYMBOL(em86xx_uart0_gpio_write);
+EXPORT_SYMBOL(em86xx_uart0_gpio_setdirection);
+#endif
+
+#if defined(CONFIG_TANGO2_UART1_AS_GPIO_FULL) || defined(CONFIG_TANGO2_UART1_AS_GPIO_PARTIAL) || defined(CONFIG_TANGO2_XENV)
+EXPORT_SYMBOL(em86xx_uart1_gpio_read);
+EXPORT_SYMBOL(em86xx_uart1_gpio_write);
+EXPORT_SYMBOL(em86xx_uart1_gpio_setdirection);
+#endif
+
+/* Given an address and length, determine if this area is physically contiguous or not, and
+   return the physical address of starting point */
+int is_contiguous_memory(unsigned long address, unsigned int len, unsigned long *physaddr)
+{
+	pgd_t *pgd;
+	pmd_t *pmd;
+	pte_t *ptep, pte;
+	struct mm_struct *mm = current->mm; /* current context only */
+	unsigned long offset, ppaddr, paddr, end, addr;
+	int ret = 0;
+
+	/* KSEG0 or KSEG1, easy conversion */
+	if ((address >= KSEG0) && (address < KSEG2)) {
+		*physaddr = paddr = CPHYSADDR(address);
+#ifdef CONFIG_TANGO2_USE_TLB_REMAP_DRAM1 /* Use TLB remap for DRAM1 */
+		return ((KSEG1ADDR(address) + len) < KSEG2) ? 1 : 0;
+#else
+		if ((paddr >= CPU_remap3_address) && (paddr < MEM_BASE_dram_controller_0)) { /* CPU_remap3/4 is used */
+			*physaddr = MEM_BASE_dram_controller_1 + (paddr - CPU_remap3_address); 
+			return ((paddr + len) < MEM_BASE_dram_controller_0) ? 1 : 0;
+		} else if (paddr >= MEM_BASE_dram_controller_0) {
+			return (KSEG1ADDR(address) + len) < KSEG2) ? 1 : 0;
+		} else {
+			return ((paddr + len) < CPU_remap3_address) ? 1 : 0;
+		}
+#endif
+	}
+
+	*physaddr = 0;
+	spin_lock(&mm->page_table_lock);
+
+	for (ppaddr = 0, end = address + len; address < end; address += PAGE_SIZE) {
+		offset = address & (PAGE_SIZE - 1);
+		addr = address & PAGE_MASK;
+
+		pgd = pgd_offset(mm, addr);
+		if (pgd_none(*pgd) || pgd_bad(*pgd))
+			goto out;
+
+		pmd = pmd_offset(pgd, addr);
+		if (pmd_none(*pmd) || pmd_bad(*pmd))
+			goto out;
+
+		ptep = pte_offset(pmd, addr);
+		if (!ptep)
+			goto out;
+
+		pte = *ptep;
+		if (!pte_present(pte)) 
+			goto out;
+
+		paddr = pte_val(pte) & PAGE_MASK;
+		if (ppaddr == 0) { /* first page */
+			ppaddr = paddr;
+			*physaddr = ppaddr | offset;
+		} else if ((ppaddr + PAGE_SIZE) != paddr) /* not contiguous */
+			goto out;
+		else
+			ppaddr = paddr;
+	}
+	ret = 1;
+
+out:
+	spin_unlock(&mm->page_table_lock);
+	return ret;
+}
+
+EXPORT_SYMBOL(is_contiguous_memory);
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/include/asm-mips/tango2/tango2api.h linuxmips-2.4.30/include/asm-mips/tango2/tango2api.h
--- linuxmips-2.4.30.ref/include/asm-mips/tango2/tango2api.h	1969-12-31 16:00:00.000000000 -0800
+++ linuxmips-2.4.30/include/asm-mips/tango2/tango2api.h	2007-02-05 14:00:28.000000000 -0800
@@ -0,0 +1,120 @@
+/*
+ * include/asm-arm/arch-em86xx/em86xxapi.h
+ *
+ * Copyright 2002-2004, Sigma Designs, Inc 
+ *
+ * This file contains EM86XX controling functions
+ *
+ * by Ho Lee 03/07/2003
+ */
+
+#ifndef __ASM_ARCH_EM86XX_H
+#define __ASM_ARCH_EM86XX_H
+#include <asm/tango2/hardware.h>
+//
+// global variables
+// 
+
+//
+// from arch/arm/arch-em86xx/irq.c
+//
+
+// irq
+void em86xx_mask_irq(unsigned int irq);
+void em86xx_unmask_irq(unsigned int irq);
+void em86xx_wait_irq(unsigned int irq);
+
+// fiq
+void em86xx_mask_fiq(unsigned int fiq);
+void em86xx_unmask_fiq(unsigned int fiq);
+
+// software interrupt
+int em86xx_softirq_isset(int irq);
+void em86xx_softirq_set(int irq);
+void em86xx_softirq_clr(int irq);
+void em86xx_irq_clr(int irq);
+
+//
+// from arch/arm/arch-em86xx/em86xxapi.c
+//
+
+// Cache
+// clean : write dirty buffer (D cache only)
+// invalidate : invalidate the contents of cache (I & D cache)
+// flush : clean + invalidate
+void em86xx_get_cache_state(int *picache, int *pdcache, int *pwriteback);
+void em86xx_enable_cache(int icache, int dcache, int writeback);
+void em86xx_clean_cache_data(void);
+void em86xx_clean_cache_data_region(unsigned int from, unsigned int to);
+void em86xx_invalidate_cache_instruction(void);
+void em86xx_invalidate_cache_instruction_region(unsigned int from, unsigned int to);
+void em86xx_invalidate_cache_data(void);
+void em86xx_invalidate_cache_data_region(unsigned int from, unsigned int to);
+
+void em86xx_flush_cache_all(void);
+void em86xx_flush_cache_data(void);
+void em86xx_flush_cache_data_region(unsigned int from, unsigned int to);
+
+// memory
+unsigned int em86xx_get_pciregionsize(void);
+unsigned int em86xx_get_dmamemorysize(void);
+
+// switchbox (Host interface)
+enum { 
+	SBOX_MBUS_W0 = 0, SBOX_MBUS_W1, SBOX_PCIMASTER, SBOX_PCISLAVE, 
+	SBOX_UNUSED1, SBOX_IDEFLASH, SBOX_IDEDVD, SBOX_UNUSED2, SBOX_MAX = SBOX_UNUSED2,
+};
+
+int em86xx_sbox_init(void);
+#if 0
+void em86xx_sbox_reset(void);
+int em86xx_sbox_setup(void);
+int em86xx_sbox_connect(int iface);
+void em86xx_sbox_disconnect(int port);
+#endif
+
+// MBUS DMA 
+typedef void (*mbus_irq_handler_t)(int irq, void *arg);
+
+int em86xx_mbus_init(void);
+unsigned int em86xx_mbus_alloc_dma(int sbox, int fromdev, unsigned int *pregbase, int *pirq);
+void em86xx_mbus_free_dma(int port);
+
+int em86xx_mbus_setup_dma_common(unsigned int regbase, int sbox, unsigned int addr, unsigned int count, mbus_irq_handler_t handler, void *arg);
+void em86xx_mbus_setup_dma_linear(unsigned int regbase, int sbox, unsigned int addr, unsigned int count);
+void em86xx_mbus_setup_dma_double(unsigned int regbase, int sbox, unsigned int addr, unsigned int count, unsigned int addr2, unsigned int count2);
+void em86xx_mbus_setup_dma_rectangle(unsigned int regbase, int sbox, unsigned int addr, unsigned int horiz, unsigned int lines, int skip);
+int em86xx_mbus_setup_dma(unsigned int regbase, int sbox, unsigned int addr, unsigned int count, mbus_irq_handler_t handler, void *arg);
+int em86xx_mbus_inuse(unsigned int regbase);
+int em86xx_mbus_wait(unsigned int regbase, int sbox);
+void em86xx_mbus_reset(unsigned int regbase, int sbox);
+
+// PCI master
+void em86xx_pcimaster_setup_read(unsigned int addr, unsigned int count);
+void em86xx_pcimaster_start_read(int start);
+void em86xx_pcimaster_setup_write(unsigned int addr, unsigned int count);
+void em86xx_pcimaster_start_write(int start);
+
+// GPIO
+#define GPIO_INPUT		0
+#define GPIO_OUTPUT		1
+
+int em86xx_gpio_read(int gpio);
+void em86xx_gpio_write(int gpio, int data);
+void em86xx_gpio_setdirection(int gpio, int dir);
+
+#if defined(CONFIG_EM86XX_UART0_AS_GPIO_FULL) || defined(CONFIG_EM86XX_UART0_AS_GPIO_PARTIAL) || defined(CONFIG_TANGO2_XENV)
+int em86xx_uart0_gpio_read(int gpio);
+void em86xx_uart0_gpio_write(int gpio, int data);
+void em86xx_uart0_gpio_setdirection(int gpio, int dir);
+#endif
+#if defined(CONFIG_EM86XX_UART1_AS_GPIO_FULL) || defined(CONFIG_EM86XX_UART1_AS_GPIO_PARTIAL) || defined(CONFIG_TANGO2_XENV)
+int em86xx_uart1_gpio_read(int gpio);
+void em86xx_uart1_gpio_write(int gpio, int data);
+void em86xx_uart1_gpio_setdirection(int gpio, int dir);
+#endif
+
+int em86xx_is_kmem(unsigned long vaddr, unsigned long *physaddr);
+
+#endif
+
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/README.1005.sbox-mbus-gpio.patch linuxmips-2.4.30/README.1005.sbox-mbus-gpio.patch
--- linuxmips-2.4.30.ref/README.1005.sbox-mbus-gpio.patch	1969-12-31 16:00:00.000000000 -0800
+++ linuxmips-2.4.30/README.1005.sbox-mbus-gpio.patch	2007-02-05 14:01:21.000000000 -0800
@@ -0,0 +1,20 @@
+Feature:
+--------
+SBOX/MBUS/GPIO common support for SMP863x.
+
+Prerequisite patch numbers:
+---------------------------
+0000
+1000
+1003
+
+Primary author:
+---------------
+YH Lin
+
+Related to which chip version SMP863x x=?
+-----------------------------------------
+all
+
+(linux patches) which CONFIG_... are provided:
+----------------------------------------------