1005.sbox-mbus-gpio.patch

sm86xx内核源包括补丁（ GPL ）的

diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/arch/mips/config-tango2.in linuxmips-2.4.30/arch/mips/config-tango2.in
--- linuxmips-2.4.30.ref/arch/mips/config-tango2.in	2007-02-05 13:59:01.000000000 -0800
+++ linuxmips-2.4.30/arch/mips/config-tango2.in	2007-02-05 14:00:28.000000000 -0800
@@ -65,5 +65,8 @@
  
 #define_bool CONFIG_UART_USE_SYSCLK y
  
+#define_bool CONFIG_SD_KEEP_SBOX_R1W1 y
+define_bool CONFIG_TANGO2_CACHE_PROC_INFO y
+ 
 endmenu
 
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/arch/mips/tango2/Makefile linuxmips-2.4.30/arch/mips/tango2/Makefile
--- linuxmips-2.4.30.ref/arch/mips/tango2/Makefile	2007-02-05 13:58:52.000000000 -0800
+++ linuxmips-2.4.30/arch/mips/tango2/Makefile	2007-02-05 14:00:28.000000000 -0800
@@ -10,9 +10,9 @@
 
 O_TARGET:= tango2.o
  
-export-objs	+= prom.o delay.o
+export-objs	+= prom.o delay.o tango2api.o
  
-obj-y    := tango2IRQ.o setup.o prom.o gbus_standalone.o irq.o tango2controllers.o delay.o 
+obj-y    := tango2IRQ.o setup.o prom.o gbus_standalone.o irq.o tango2controllers.o delay.o tango2api.o
 
 ifdef CONFIG_TANGO2_XENV
 obj-y	+= sha1sum.o xenv.o full_sha1.o
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/arch/mips/tango2/setup.c linuxmips-2.4.30/arch/mips/tango2/setup.c
--- linuxmips-2.4.30.ref/arch/mips/tango2/setup.c	2007-02-05 13:58:52.000000000 -0800
+++ linuxmips-2.4.30/arch/mips/tango2/setup.c	2007-02-05 14:00:28.000000000 -0800
@@ -210,5 +210,8 @@
 	ioport_resource.start = iomem_resource.start = 0x0;
 	ioport_resource.end = 0x80000000UL - 1;
 	iomem_resource.end = 0x80000000UL - 1;
+
+  	/* Initialize Switch box */
+  	em86xx_sbox_init();
 }
 
diff -Naur --exclude=CVS --exclude='*.o' --exclude='*.a' --exclude='*.so' --exclude='*.elf' --exclude=System.map --exclude=Makefile.d --exclude='*log' --exclude='*log2' --exclude='*~' --exclude='.*~' --exclude='.#*' --exclude='*.bak' --exclude='*.orig' --exclude='*.rej' --exclude='core.[0-9]*' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=.depend --exclude='.*.o.flags' --exclude='*.gz' --exclude=vmlinux --exclude=vmlinux.bin --exclude=yamon-02.06-SIGMADESIGNS-01_el.bin linuxmips-2.4.30.ref/arch/mips/tango2/tango2api.c linuxmips-2.4.30/arch/mips/tango2/tango2api.c
--- linuxmips-2.4.30.ref/arch/mips/tango2/tango2api.c	1969-12-31 16:00:00.000000000 -0800
+++ linuxmips-2.4.30/arch/mips/tango2/tango2api.c	2007-02-05 14:00:39.000000000 -0800
@@ -0,0 +1,781 @@
+/*****************************************
+ Copyright 漏 2001-2003  
+ Sigma Designs, Inc. All Rights Reserved
+ Proprietary and Confidential
+ *****************************************/
+/**
+  @file  tango2api.c
+  @brief  
+
+  Misc. support for Tango2.
+
+  @author YH Lin
+  @date   2005-01-20
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/tango2/rmdefs.h>
+#include <asm/tango2/memcfg.h>
+#include <asm/tango2/hardware.h>
+#include <asm/tango2/tango2api.h>
+#include <asm/io.h>
+#include <asm/wbflush.h>
+#include <asm/pgalloc.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+
+#if (EM86XX_REVISION > 3)
+
+#ifdef CONFIG_TANGO2_CACHE_PROC_INFO
+#include <linux/proc_fs.h>
+
+extern unsigned long em8xxx_cpu_frequency;
+static int cpucache_info_read_proc(char *buf, char **start, off_t off, int count, int *eof, void *data);
+static unsigned long cpucache_saved_jiffies = 0;
+static unsigned icache_missed = 0, dcache_missed = 0;
+#endif
+#endif /* EM86XX_REVISION > 3 */
+
+#ifdef CONFIG_TANGO2_USE_TLB_REMAP_DRAM1
+/* For Use TLB mapping to map the DRAM1 into KSEG2 */
+extern unsigned long em86xx_tlb_dram1_map_base;
+extern unsigned long em86xx_tlb_dram1_map_size;
+#endif
+
+
+//
+// global variables
+//
+
+//
+// init
+//
+ 
+extern unsigned long em8xxx_kmem_start;
+extern unsigned long em8xxx_kmem_size;
+
+int __init em86xx_init(void)
+{
+	em86xx_mbus_init();
+
+#if !defined(CONFIG_TANGO2_XENV)
+#ifdef CONFIG_TANGO2_UART0_AS_GPIO_FULL
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_uart0_gpio_mode, 0x7f7f);
+#endif
+#ifdef CONFIG_TANGO2_UART0_AS_GPIO_PARTIAL
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_uart0_gpio_mode, 0x7f6e);
+#endif
+#ifdef CONFIG_TANGO2_UART1_AS_GPIO_FULL
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_uart1_gpio_mode, 0x7f7f);
+#endif
+#ifdef CONFIG_TANGO2_UART1_AS_GPIO_PARTIAL
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_uart1_gpio_mode, 0x7f6e);
+#endif
+#endif /* !CONFIG_TANGO2_XENV */
+
+#if defined(CONFIG_BLK_DEV_TANGO2_BMIDEDMA) || defined(CONFIG_BLK_DEV_TANGO2_ISAIDEDMA)
+	/* Maximum MBUS bandwidth for IDE */
+	gbus_write_uint32(pGBus, REG_BASE_system_block + MARB_mid02_cfg, 0x11f1f);
+	gbus_write_uint32(pGBus, REG_BASE_system_block + MARB_mid22_cfg, 0x11f1f);
+#endif
+
+#if (EM86XX_REVISION > 3)
+#ifdef CONFIG_TANGO2_CACHE_PROC_INFO
+	create_proc_read_entry("cpucache_info", S_IRUGO, NULL,
+			cpucache_info_read_proc, NULL);
+
+	/* Enable performance monitor and start counting */
+	/* 0: DCache Hit 
+	 * 1: DCache Miss
+	 * 2: TLB Hit
+	 * 3: TLB Miss
+	 * 4: ICache Hit
+	 * 5: ICache Miss
+	 * 6: Instn Complete
+	 * 7: ITLB Hit
+	 * 8: ITLB Miss
+	 * 9: JTLB Hit
+	 * 10: JTLB Miss
+	 * 11: WTB Merge */
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_pm_select_1, (1<<5));
+	gbus_write_uint32(pGBus, REG_BASE_cpu_block + CPU_pm_select_0, (1<<1));
+	cpucache_saved_jiffies = jiffies;
+	icache_missed = gbus_read_uint32(pGBus, REG_BASE_cpu_block + CPU_pm_counter_1);
+	dcache_missed = gbus_read_uint32(pGBus, REG_BASE_cpu_block + CPU_pm_counter_0);
+#endif
+
+#ifdef CONFIG_TANGO2_USE_TLB_REMAP_DRAM1 /* Use TLB remap for DRAM1 */
+	{
+		/* Use TLB mapping to map the DRAM1 (size specified by memcfg) into KSEG2 */
+		memcfg_t *m=(memcfg_t *)KSEG1ADDR(MEM_BASE_dram_controller_0+FM_MEMCFG);
+		em86xx_tlb_dram1_map_base = (unsigned long)ioremap(MEM_BASE_dram_controller_1, m->dram1_size);
+		em86xx_tlb_dram1_map_size = m->dram1_size;
+		printk("Creating TLB mapping for 0x%08lx to 0x%08lx, size 0x%08lx.\n", MEM_BASE_dram_controller_1,
+				em86xx_tlb_dram1_map_base, em86xx_tlb_dram1_map_size);
+	}
+#else
+	// remap strategy (use CPU_remap3/4 for 128MB resolution)
+	{
+		printk("Creating CPU mapping for 0x%08lx to 0x%08lx, size 0x%08lx.\n", MEM_BASE_dram_controller_1,
+				CPU_remap3_address, 0x08000000);
+		gbus_write_uint32(pGBus, REG_BASE_cpu_block+CPU_remap3, MEM_BASE_dram_controller_1);
+		gbus_write_uint32(pGBus, REG_BASE_cpu_block+CPU_remap4, MEM_BASE_dram_controller_1+0x04000000);
+		iob() ; // beware bug #4570
+	}
+#endif
+#endif /* EM86XX_REVISION > 3 */
+	return 0;
+}
+
+__initcall(em86xx_init);
+
+#if (EM86XX_REVISION > 3)
+#ifdef CONFIG_TANGO2_CACHE_PROC_INFO
+static int cpucache_info_read_proc(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+        int len = 0;
+	unsigned long diffj, diffi, diffd, icache_miss, dcache_miss, tmpj;
+	unsigned long pd, pi;
+        
+	icache_miss = gbus_read_uint32(pGBus, REG_BASE_cpu_block + CPU_pm_counter_1);
+	dcache_miss = gbus_read_uint32(pGBus, REG_BASE_cpu_block + CPU_pm_counter_0);
+	tmpj = jiffies;
+	diffj = tmpj - cpucache_saved_jiffies; 
+	cpucache_saved_jiffies = tmpj;
+	if (diffj == 0)
+		diffj = 1;
+
+	if (icache_miss < icache_missed)
+		diffi = (0xffffffff - icache_missed) + icache_miss;
+	else
+		diffi = icache_miss - icache_missed;
+	icache_missed = icache_miss;
+
+	if (dcache_miss < dcache_missed)
+		diffd = (0xffffffff - dcache_missed) + dcache_miss;
+	else
+		diffd = dcache_miss - dcache_missed;
+	dcache_missed = dcache_miss;
+
+	len += sprintf(page+off+len, "jiffies");
+	/* The average miss per jiffies is (diffx / diffj), per second is then ((diffx * HZ) / diffj).
+	 * Assuming one instruction per clock, we have (((diffx * HZ) / diffj) / em8xxx_cpu_frequency)
+	 * as average ratio of cache miss per instruction at given period of time (from last 
+	 * measured, as expressed as (diffj / HZ)). */
+	pi = ((diffi * HZ) / diffj) / (em8xxx_cpu_frequency / 10000); /* Times 10000 to get percentage */
+	pd = ((diffd * HZ) / diffj) / (em8xxx_cpu_frequency / 10000);
+
+	len += sprintf(page+off+len, "(%ld): I-Cache miss ratio(%ld): %ld.%02ld%c, D-Cache miss ratio(%ld): %ld.%02ld%c\n",
+			diffj, diffi, pi / 100, pi % 100, '%', diffd, pd / 100, pd % 100, '%');
+	*eof = 1;
+        return(len);
+}
+#endif
+#endif
+
+//
+// switchbox
+// 
+
+static int g_sbox_map[SBOX_MAX + 1];
+static int lastiface = -1;
+
+static int em86xx_sbox_setup(void);
+static void em86xx_sbox_reset(void);
+
+// Initialize SwitchBox 
+int em86xx_sbox_init(void)
+{
+	em86xx_sbox_setup();
+	em86xx_sbox_reset();
+
+	return 0;
+}
+
+static void em86xx_sbox_reset(void)
+{
+	/* Leave W1/R1 alone. */
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + SBOX_FIFO_RESET, 0x7d7dfdfd);
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + SBOX_FIFO_RESET, 0x7d00fd00);
+}
+
+static int em86xx_sbox_setup(void)
+{
+	int i;
+	unsigned int data;
+
+	g_sbox_map[0] = 0xf; /* W0 initially disconnected */
+	g_sbox_map[1] = 0; /* Leave W1 alone */
+
+	g_sbox_map[SBOX_PCIMASTER] = 0xf;
+	g_sbox_map[SBOX_PCISLAVE] = SBOX_PCISLAVE + 1; /* Loopback */
+	g_sbox_map[SBOX_UNUSED1] = 0xf;
+	g_sbox_map[SBOX_IDEDVD] = 0xf;
+	g_sbox_map[SBOX_IDEFLASH] = 0xf;
+	g_sbox_map[SBOX_UNUSED2] = 0xf;
+
+	for (i = SBOX_MAX, data = 0; i >= 0; --i)
+		data = (data << 4) | g_sbox_map[i];
+
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + SBOX_ROUTE, data);
+	return 0;
+}
+
+/* Connect given interface to R0/W0 channel */
+static int em86xx_sbox_connect(int iface)
+{
+	unsigned int data;
+	int flags, i;
+
+	/* Already connected? */
+	if ((g_sbox_map[0] == iface + 1) && (g_sbox_map[iface] = 1))
+		return(0);
+	else if ((g_sbox_map[0] != 0xf) || (g_sbox_map[iface] != 0xf))
+		return(-1); /* Been occupied */
+
+	local_irq_save(flags);
+	g_sbox_map[0] = iface + 1;
+	g_sbox_map[iface] = 1;
+	lastiface = iface;
+
+	for (i = SBOX_MAX, data = 0; i >= 0; --i)
+		data = (data << 4) | g_sbox_map[i];
+	gbus_write_uint32(pGBus, REG_BASE_host_interface + SBOX_ROUTE, data);
+	local_irq_restore(flags);
+	return(0);
+}
+
+static void em86xx_sbox_disconnect(int port)
+{
+	unsigned int data;
+	int flags, i;
+
+	if ((port >= 0) && (lastiface >= 0)) {
+		local_irq_save(flags);
+		g_sbox_map[0] = 0xf;
+		g_sbox_map[lastiface] = 0xf;
+		lastiface = -1;
+		for (i = SBOX_MAX, data = 0; i >= 0; --i)
+			data = (data << 4) | g_sbox_map[i];
+		gbus_write_uint32(pGBus, REG_BASE_host_interface + SBOX_ROUTE, data);
+		local_irq_restore(flags);
+	}
+}
+
+//
+// MBUS interface 
+// 
+
+static int s_mbus_irq_inited[4] = {0,0,0,0};
+static mbus_irq_handler_t s_mbus_irq_handler[4] = {0,0,0,0};
+static void *s_mbus_irq_handler_arg[4] = {NULL, NULL, NULL, NULL};
+
+static void em86xx_mbus_init_irq(int irq);
+static void em86xx_mbus_irq(int irq, void *devinfo, struct pt_regs *regs);
+
+int em86xx_mbus_init(void)
+{